Searched refs:AndOp0 (Results 1 – 3 of 3) sorted by relevance
/external/llvm-project/llvm/lib/Transforms/AggressiveInstCombine/ |
D | AggressiveInstCombine.cpp | 310 Value *AndOp0; in tryToRecognizePopCount() local 313 m_c_Add(m_And(m_Value(AndOp0), m_SpecificInt(Mask33)), in tryToRecognizePopCount() 314 m_And(m_LShr(m_Deferred(AndOp0), m_SpecificInt(2)), in tryToRecognizePopCount() 318 if (match(AndOp0, m_Sub(m_Value(Root), m_Value(SubOp1))) && in tryToRecognizePopCount()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/AggressiveInstCombine/ |
D | AggressiveInstCombine.cpp | 295 Value *AndOp0; in tryToRecognizePopCount() local 298 m_c_Add(m_And(m_Value(AndOp0), m_SpecificInt(Mask33)), in tryToRecognizePopCount() 299 m_And(m_LShr(m_Deferred(AndOp0), m_SpecificInt(2)), in tryToRecognizePopCount() 303 if (match(AndOp0, m_Sub(m_Value(Root), m_Value(SubOp1))) && in tryToRecognizePopCount()
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | DAGCombiner.cpp | 1745 SDValue AndOp0 = N1.getOperand(0); in visitADD() local 1746 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); in visitADD() 1753 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); in visitADD()
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