| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SILowerControlFlow.cpp | 375 Register AndReg = MRI->createVirtualRegister(BoolRC); in emitIfBreak() local
376 And = BuildMI(MBB, &MI, DL, TII->get(AndOpc), AndReg) in emitIfBreak()
380 .addReg(AndReg) in emitIfBreak()
383 LIS->createAndComputeVirtRegInterval(AndReg); in emitIfBreak()
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| D | AMDGPURegisterBankInfo.cpp | 872 Register AndReg = MRI.createVirtualRegister(WaveRC); in executeInWaterfallLoop() local
876 .addDef(AndReg) in executeInWaterfallLoop()
879 CondReg = AndReg; in executeInWaterfallLoop()
965 Register AndReg = MRI.createVirtualRegister(WaveRC); in executeInWaterfallLoop() local
969 .addDef(AndReg) in executeInWaterfallLoop()
972 CondReg = AndReg; in executeInWaterfallLoop()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SILowerControlFlow.cpp | 413 Register AndReg = MRI->createVirtualRegister(BoolRC); in emitIfBreak() local
414 And = BuildMI(MBB, &MI, DL, TII->get(AndOpc), AndReg) in emitIfBreak()
418 .addReg(AndReg) in emitIfBreak()
421 LIS->createAndComputeVirtRegInterval(AndReg); in emitIfBreak()
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| D | AMDGPURegisterBankInfo.cpp | 893 Register AndReg = MRI.createVirtualRegister(WaveRC); in executeInWaterfallLoop() local
897 .addDef(AndReg) in executeInWaterfallLoop()
900 CondReg = AndReg; in executeInWaterfallLoop()
986 Register AndReg = MRI.createVirtualRegister(WaveRC); in executeInWaterfallLoop() local
990 .addDef(AndReg) in executeInWaterfallLoop()
993 CondReg = AndReg; in executeInWaterfallLoop()
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| D | SIInstrInfo.cpp | 4897 Register AndReg = MRI.createVirtualRegister(BoolXExecRC); in emitLoadSRsrcFromVGPRLoop() local
4898 BuildMI(LoopBB, I, DL, TII.get(AndOpc), AndReg) in emitLoadSRsrcFromVGPRLoop()
4901 CondReg = AndReg; in emitLoadSRsrcFromVGPRLoop()
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| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | CombinerHelper.cpp | 3066 Register AndReg = MI.getOperand(1).getReg(); in matchXorOfAndWithSameReg() local
3074 if (!mi_match(AndReg, MRI, m_GAnd(m_Reg(X), m_Reg(Y)))) { in matchXorOfAndWithSameReg()
3075 std::swap(AndReg, SharedReg); in matchXorOfAndWithSameReg()
3076 if (!mi_match(AndReg, MRI, m_GAnd(m_Reg(X), m_Reg(Y)))) in matchXorOfAndWithSameReg()
3081 if (!MRI.hasOneNonDBGUse(AndReg)) in matchXorOfAndWithSameReg()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 412 Register AndReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass); in LowerFPToInt() local
416 BuildMI(BB, DL, TII.get(And), AndReg).addReg(CmpReg).addReg(SecondCmpReg); in LowerFPToInt()
417 CmpReg = AndReg; in LowerFPToInt()
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| /external/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 402 Register AndReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass); in LowerFPToInt() local
406 BuildMI(BB, DL, TII.get(And), AndReg).addReg(CmpReg).addReg(SecondCmpReg); in LowerFPToInt()
407 CmpReg = AndReg; in LowerFPToInt()
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 2149 unsigned AndReg = fastEmitInst_rr(Opc[1], RC, CmpReg, /*IsKill=*/false, in X86FastEmitSSESelect() local
2154 AndReg, /*IsKill=*/true); in X86FastEmitSSESelect()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 2284 Register AndReg = fastEmitInst_rr(Opc[1], VR128, CmpReg, in X86FastEmitSSESelect() local
2289 AndReg, /*Op1IsKill=*/true); in X86FastEmitSSESelect()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 2268 unsigned AndReg = fastEmitInst_rr(Opc[1], VR128, CmpReg, /*IsKill=*/false, in X86FastEmitSSESelect() local
2273 AndReg, /*IsKill=*/true); in X86FastEmitSSESelect()
|