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Searched refs:AreConsecutive (Results 1 – 5 of 5) sorted by relevance

/external/vixl/test/aarch64/
Dtest-api-aarch64.cc514 VIXL_CHECK(AreConsecutive(b0, NoVReg)); in TEST()
515 VIXL_CHECK(AreConsecutive(b1, b2)); in TEST()
516 VIXL_CHECK(AreConsecutive(b3, b4, b5)); in TEST()
517 VIXL_CHECK(AreConsecutive(b6, b7, b8, b9)); in TEST()
518 VIXL_CHECK(AreConsecutive(h10, NoVReg)); in TEST()
519 VIXL_CHECK(AreConsecutive(h11, h12)); in TEST()
520 VIXL_CHECK(AreConsecutive(h13, h14, h15)); in TEST()
521 VIXL_CHECK(AreConsecutive(h16, h17, h18, h19)); in TEST()
522 VIXL_CHECK(AreConsecutive(s20, NoVReg)); in TEST()
523 VIXL_CHECK(AreConsecutive(s21, s22)); in TEST()
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/external/vixl/src/aarch64/
Dassembler-aarch64.cc341 VIXL_ASSERT(AreConsecutive(vn, vn2)); in tbl()
354 VIXL_ASSERT(AreConsecutive(vn, vn2, vn3)); in tbl()
368 VIXL_ASSERT(AreConsecutive(vn, vn2, vn3, vn4)); in tbl()
388 VIXL_ASSERT(AreConsecutive(vn, vn2)); in tbx()
401 VIXL_ASSERT(AreConsecutive(vn, vn2, vn3)); in tbx()
415 VIXL_ASSERT(AreConsecutive(vn, vn2, vn3, vn4)); in tbx()
1705 VIXL_ASSERT(AreConsecutive(rs, rs1)); \ in COMPARE_AND_SWAP_W_LIST()
1706 VIXL_ASSERT(AreConsecutive(rt, rt1)); \ in COMPARE_AND_SWAP_W_LIST()
2063 VIXL_ASSERT(AreConsecutive(vt, vt2)); in ld1()
2075 VIXL_ASSERT(AreConsecutive(vt, vt2, vt3)); in ld1()
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Dregisters-aarch64.cc264 bool AreConsecutive(const CPURegister& reg1, in AreConsecutive() function
Dregisters-aarch64.h875 bool AreConsecutive(const CPURegister& reg1,
Dassembler-sve-aarch64.cc4058 VIXL_ASSERT(AreConsecutive(zt1, zt2)); \
4071 VIXL_ASSERT(AreConsecutive(zt1, zt2, zt3)); \
4085 VIXL_ASSERT(AreConsecutive(zt1, zt2, zt3, zt4)); \
5116 VIXL_ASSERT(AreConsecutive(zt1, zt2)); \
5129 VIXL_ASSERT(AreConsecutive(zt1, zt2, zt3)); \
5143 VIXL_ASSERT(AreConsecutive(zt1, zt2, zt3, zt4)); \