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Searched refs:AreSameFormat (Results 1 – 8 of 8) sorted by relevance

/external/vixl/src/aarch64/
Dassembler-aarch64.cc321 VIXL_ASSERT(AreSameFormat(vd, vm)); in NEONTable()
340 VIXL_ASSERT(AreSameFormat(vn, vn2)); in tbl()
353 VIXL_ASSERT(AreSameFormat(vn, vn2, vn3)); in tbl()
367 VIXL_ASSERT(AreSameFormat(vn, vn2, vn3, vn4)); in tbl()
387 VIXL_ASSERT(AreSameFormat(vn, vn2)); in tbx()
400 VIXL_ASSERT(AreSameFormat(vn, vn2, vn3)); in tbx()
414 VIXL_ASSERT(AreSameFormat(vn, vn2, vn3, vn4)); in tbx()
1656 VIXL_ASSERT(AreSameFormat(rs, rt)); \
1707 VIXL_ASSERT(AreSameFormat(rs, rs1, rt, rt1)); \ in COMPARE_AND_SWAP_W_LIST()
2062 VIXL_ASSERT(AreSameFormat(vt, vt2)); in ld1()
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Dassembler-sve-aarch64.cc135 VIXL_ASSERT(AreSameFormat(zd, zn, zm)); in and_()
144 VIXL_ASSERT(AreSameFormat(zd, zn, zm)); in bic()
153 VIXL_ASSERT(AreSameFormat(zd, zn, zm)); in eor()
162 VIXL_ASSERT(AreSameFormat(zd, zn, zm)); in orr()
2325 VIXL_ASSERT(AreSameFormat(zd, zn, zm)); in add()
2341 VIXL_ASSERT(AreSameFormat(zd, zn, zm)); in and_()
2357 VIXL_ASSERT(AreSameFormat(zd, zn, zm)); in bic()
2373 VIXL_ASSERT(AreSameFormat(zd, zn, zm)); in eor()
2389 VIXL_ASSERT(AreSameFormat(zd, zn, zm)); in mul()
2405 VIXL_ASSERT(AreSameFormat(zd, zn, zm)); in orr()
[all …]
Dregisters-aarch64.cc294 bool AreSameFormat(const CPURegister& reg1, in AreSameFormat() function
Dregisters-aarch64.h883 bool AreSameFormat(const CPURegister& reg1,
Doperands-aarch64.h608 AreSameFormat(base_, regoffset_) && in IsVectorPlusVector()
Dmacro-assembler-aarch64.h4029 VIXL_ASSERT(AreSameFormat(zd, zn)); in Decp()
4753 VIXL_ASSERT(AreSameFormat(zd, zn)); in Incp()
5739 VIXL_ASSERT(AreSameFormat(zd, zn)); in Sqdecp()
5828 VIXL_ASSERT(AreSameFormat(zd, zn)); in Sqincp()
6163 VIXL_ASSERT(AreSameFormat(zd, zn)); in Uqdecp()
6227 VIXL_ASSERT(AreSameFormat(zd, zn)); in Uqincp()
Dmacro-assembler-sve-aarch64.cc993 VIXL_ASSERT(AreSameFormat(pd, pn)); in Pnext()
/external/vixl/test/aarch64/
Dtest-utils-aarch64.h456 VIXL_ASSERT(AreSameFormat(expected, result)); in EqualSVE()