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Searched refs:AreSameLaneSize (Results 1 – 5 of 5) sorted by relevance

/external/vixl/src/aarch64/
Dassembler-sve-aarch64.cc54 AreSameLaneSize(zd, addr.GetVectorBase(), addr.GetVectorOffset())); in adr()
208 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm) || in asr()
212 if (AreSameLaneSize(zd, zn, zm)) { in asr()
248 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm)); in asrr()
283 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm) || in lsl()
287 if (AreSameLaneSize(zd, zn, zm)) { in lsl()
305 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm)); in lslr()
340 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm) || in lsr()
344 if (AreSameLaneSize(zd, zn, zm)) { in lsr()
362 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm)); in lsrr()
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Dregisters-aarch64.cc306 bool AreSameLaneSize(const CPURegister& reg1, in AreSameLaneSize() function
Dregisters-aarch64.h893 bool AreSameLaneSize(const CPURegister& reg1,
Dmacro-assembler-aarch64.h562 VIXL_ASSERT(AreSameLaneSize(dst, src)); in ShouldGenerateMovprfx()
3517 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm)); in And()
3574 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm)); in Bic()
4086 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm)); in Eor()
5453 VIXL_ASSERT(AreSameLaneSize(zd, zn, zm)); in Orr()
/external/vixl/test/aarch64/
Dtest-assembler-sve-aarch64.cc11966 VIXL_ASSERT(AreSameLaneSize(dst, src)); in IntSegmentPatternHelper()
14853 VIXL_ASSERT(AreSameLaneSize(dst, src)); in FPSegmentPatternHelper()