| /external/llvm/test/CodeGen/Mips/ |
| D | assertzext-trunc.ll | 17 ; (AssertZext:i32 (trunc:i32 (AssertZext:i64 X, i32)), i8)
35 ; Check that we do sign-extend when we have a (trunc:i32 (AssertZext:i64 X, i32))
|
| /external/llvm-project/llvm/test/CodeGen/Mips/ |
| D | assertzext-trunc.ll | 17 ; (AssertZext:i32 (trunc:i32 (AssertZext:i64 X, i32)), i8)
35 ; Check that we do sign-extend when we have a (trunc:i32 (AssertZext:i64 X, i32))
|
| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | TruncAssertZext.ll | 4 ; the source of the zext is an AssertZext node
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 57 AssertSext, AssertZext, enumerator
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 58 AssertSext, AssertZext, enumerator
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 60 AssertZext, enumerator
|
| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | zext-lid.ll | 55 ; which is a special case as an AssertZext from width 0 is invalid.
|
| D | captured-frame-index.ll | 181 ; on the leftover AssertZext's ValueType operand.
|
| D | function-returns.ll | 474 ; AssertZext inserted. Not using it introduces the spills.
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 86 case ISD::AssertZext: return "AssertZext"; in getOperationName()
|
| D | LegalizeIntegerTypes.cpp | 54 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; in PromoteIntegerResult()
182 return DAG.getNode(ISD::AssertZext, SDLoc(N), in PromoteIntRes_AssertZext()
436 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res, in PromoteIntRes_FP_TO_XINT()
1313 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; in ExpandIntegerResult()
1919 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi, in ExpandIntRes_AssertZext()
1923 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT)); in ExpandIntRes_AssertZext()
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 193 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonPatterns.td | 718 def AssertZextSD: SDNode<"ISD::AssertZext", SDTAssertZext>;
719 class AssertZext<ValueType T>: PatFrag<(ops node:$A), (AssertZextSD $A, T)>;
746 defm: Cmpb_pat <A4_cmpbeqi, seteq, AssertZext<i8>, IsUGT<8,31>, 255>;
747 defm: CmpbN_pat <A4_cmpbeqi, setne, AssertZext<i8>, IsUGT<8,31>, 255>;
748 defm: Cmpb_pat <A4_cmpbgtui, setugt, AssertZext<i8>, IsUGT<32,31>, 255>;
749 defm: CmpbN_pat <A4_cmpbgtui, setule, AssertZext<i8>, IsUGT<32,31>, 255>;
750 defm: Cmpb_pat <A4_cmphgtui, setugt, AssertZext<i16>, IsUGT<32,31>, 65535>;
751 defm: CmpbN_pat <A4_cmphgtui, setule, AssertZext<i16>, IsUGT<32,31>, 65535>;
752 defm: CmpbND_pat<A4_cmpbgtui, setult, AssertZext<i8>, IsUGT<32,32>, 255>;
753 defm: CmpbND_pat<A4_cmphgtui, setult, AssertZext<i16>, IsUGT<32,32>, 65535>;
|
| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonPatterns.td | 748 def AssertZextSD: SDNode<"ISD::AssertZext", SDTAssertZext>;
749 class AssertZext<ValueType T>: PatFrag<(ops node:$A), (AssertZextSD $A, T)>;
776 defm: Cmpb_pat <A4_cmpbeqi, seteq, AssertZext<i8>, IsUGT<8,31>, 255>;
777 defm: CmpbN_pat <A4_cmpbeqi, setne, AssertZext<i8>, IsUGT<8,31>, 255>;
778 defm: Cmpb_pat <A4_cmpbgtui, setugt, AssertZext<i8>, IsUGT<32,31>, 255>;
779 defm: CmpbN_pat <A4_cmpbgtui, setule, AssertZext<i8>, IsUGT<32,31>, 255>;
780 defm: Cmpb_pat <A4_cmphgtui, setugt, AssertZext<i16>, IsUGT<32,31>, 65535>;
781 defm: CmpbN_pat <A4_cmphgtui, setule, AssertZext<i16>, IsUGT<32,31>, 65535>;
782 defm: CmpbND_pat<A4_cmpbgtui, setult, AssertZext<i8>, IsUGT<32,32>, 255>;
783 defm: CmpbND_pat<A4_cmphgtui, setult, AssertZext<i16>, IsUGT<32,32>, 65535>;
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 427 setTargetDAGCombine(ISD::AssertZext); in MipsTargetLowering()
816 if (N0.getOperand(0).getOpcode() != ISD::AssertZext) in performAssertZextCombine()
829 ISD::AssertZext, SDLoc(N), WiderAssertZext.getValueType(), in performAssertZextCombine()
859 case ISD::AssertZext: in PerformDAGCombine()
2943 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, in LowerCallResult()
3005 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); in UnpackFromArgumentSlot()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 250 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 108 case ISD::AssertZext: return "AssertZext"; in getOperationName()
|
| D | LegalizeIntegerTypes.cpp | 57 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; in PromoteIntegerResult()
224 return DAG.getNode(ISD::AssertZext, SDLoc(N), in PromoteIntRes_AssertZext()
546 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res, in PromoteIntRes_FP_TO_XINT()
1804 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; in ExpandIntegerResult()
2558 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi, in ExpandIntRes_AssertZext()
2562 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT)); in ExpandIntRes_AssertZext()
|
| /external/llvm-project/llvm/lib/Target/VE/ |
| D | VEISelLowering.cpp | 391 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, in LowerFormalArguments()
743 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV, in LowerCall()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 762 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg, in LowerFormalArguments()
1311 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, TFI, in LowerFrameIndex()
1631 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Param, in lowerImplicitZextParam()
3186 if (Op.getOpcode() == ISD::AssertZext) in isFrameIndexOp()
|
| /external/llvm-project/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 283 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 437 Opc != ISD::AssertZext; in isDef32()
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 108 case ISD::AssertZext: return "AssertZext"; in getOperationName()
|
| D | LegalizeIntegerTypes.cpp | 57 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; in PromoteIntegerResult()
247 return DAG.getNode(ISD::AssertZext, SDLoc(N), in PromoteIntRes_AssertZext()
595 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res, in PromoteIntRes_FP_TO_XINT()
2032 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; in ExpandIntegerResult()
2835 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi, in ExpandIntRes_AssertZext()
2839 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT)); in ExpandIntRes_AssertZext()
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 458 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
|