| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | InlineAsmLowering.cpp | 99 Register AssignedReg; in getRegistersForValue() local
101 std::tie(AssignedReg, RC) = TLI.getRegForInlineAsmConstraint( in getRegistersForValue()
127 if (AssignedReg) { in getRegistersForValue()
128 for (; *I != AssignedReg; ++I) in getRegistersForValue()
136 Register R = AssignedReg ? Register(*I) : RegInfo.createVirtualRegister(RC); in getRegistersForValue()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 608 unsigned AssignedReg = FuncInfo.ValueMap[I]; in SelectLoad() local
610 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr; in SelectLoad()
1094 unsigned AssignedReg = FuncInfo.ValueMap[I]; in PPCMoveToIntReg() local
1096 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr; in PPCMoveToIntReg()
1183 unsigned AssignedReg = FuncInfo.ValueMap[I]; in SelectBinaryIntOp() local
1185 (AssignedReg ? MRI.getRegClass(AssignedReg) : in SelectBinaryIntOp()
1836 unsigned AssignedReg = FuncInfo.ValueMap[I]; in SelectIntExt() local
1838 (AssignedReg ? MRI.getRegClass(AssignedReg) : in SelectIntExt()
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 612 unsigned AssignedReg = FuncInfo.ValueMap[I]; in SelectLoad() local
614 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr; in SelectLoad()
1177 unsigned AssignedReg = FuncInfo.ValueMap[I]; in PPCMoveToIntReg() local
1179 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr; in PPCMoveToIntReg()
1283 unsigned AssignedReg = FuncInfo.ValueMap[I]; in SelectBinaryIntOp() local
1285 (AssignedReg ? MRI.getRegClass(AssignedReg) : in SelectBinaryIntOp()
1928 unsigned AssignedReg = FuncInfo.ValueMap[I]; in SelectIntExt() local
1930 (AssignedReg ? MRI.getRegClass(AssignedReg) : in SelectIntExt()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 611 unsigned AssignedReg = FuncInfo.ValueMap[I]; in SelectLoad() local
613 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr; in SelectLoad()
1175 unsigned AssignedReg = FuncInfo.ValueMap[I]; in PPCMoveToIntReg() local
1177 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr; in PPCMoveToIntReg()
1280 unsigned AssignedReg = FuncInfo.ValueMap[I]; in SelectBinaryIntOp() local
1282 (AssignedReg ? MRI.getRegClass(AssignedReg) : in SelectBinaryIntOp()
1921 unsigned AssignedReg = FuncInfo.ValueMap[I]; in SelectIntExt() local
1923 (AssignedReg ? MRI.getRegClass(AssignedReg) : in SelectIntExt()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUTargetTransformInfo.cpp | 860 Register AssignedReg; in isInlineAsmSourceOfDivergence() local
862 std::tie(AssignedReg, RC) = TLI->getRegForInlineAsmConstraint( in isInlineAsmSourceOfDivergence()
864 if (AssignedReg) { in isInlineAsmSourceOfDivergence()
867 RC = TRI->getPhysRegClass(AssignedReg); in isInlineAsmSourceOfDivergence()
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| D | SIISelLowering.cpp | 11946 unsigned AssignedReg; in requiresUniformRegister() local
11948 std::tie(AssignedReg, RC) = getRegForInlineAsmConstraint( in requiresUniformRegister()
11952 if (AssignedReg != 0 && SIRI->isSGPRReg(MRI, AssignedReg)) in requiresUniformRegister()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | RegAllocFast.cpp | 225 MCPhysReg AssignedReg, bool Kill);
316 MCPhysReg AssignedReg, bool Kill) { in spill() argument
318 << " in " << printReg(AssignedReg, TRI)); in spill()
323 TII->storeRegToStackSlot(*MBB, Before, AssignedReg, Kill, FI, &RC, TRI); in spill()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | RegAllocFast.cpp | 260 MCPhysReg AssignedReg, bool Kill, bool LiveOut);
389 MCPhysReg AssignedReg, bool Kill, bool LiveOut) { in spill() argument
391 << " in " << printReg(AssignedReg, TRI)); in spill()
396 TII->storeRegToStackSlot(*MBB, Before, AssignedReg, Kill, FI, &RC, TRI); in spill()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 304 unsigned &AssignedReg = FuncInfo.ValueMap[I]; in updateValueMap() local
305 if (AssignedReg == 0) in updateValueMap()
307 AssignedReg = Reg; in updateValueMap()
308 else if (Reg != AssignedReg) { in updateValueMap()
311 FuncInfo.RegFixups[AssignedReg + i] = Reg + i; in updateValueMap()
313 AssignedReg = Reg; in updateValueMap()
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| D | SelectionDAGBuilder.cpp | 6511 if (unsigned AssignedReg = PhysReg.first) { in GetRegistersForValue() local
6522 Regs.push_back(AssignedReg); in GetRegistersForValue()
6527 for (; *I != AssignedReg; ++I) in GetRegistersForValue()
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 506 Register &AssignedReg = FuncInfo.ValueMap[I]; in updateValueMap() local
507 if (!AssignedReg) in updateValueMap()
509 AssignedReg = Reg; in updateValueMap()
510 else if (Reg != AssignedReg) { in updateValueMap()
513 FuncInfo.RegFixups[AssignedReg + i] = Reg + i; in updateValueMap()
517 AssignedReg = Reg; in updateValueMap()
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| D | SelectionDAGBuilder.cpp | 7997 unsigned AssignedReg; in GetRegistersForValue() local
7999 std::tie(AssignedReg, RC) = TLI.getRegForInlineAsmConstraint( in GetRegistersForValue()
8070 if (AssignedReg) { in GetRegistersForValue()
8071 for (; *I != AssignedReg; ++I) in GetRegistersForValue()
8077 Register R = AssignedReg ? Register(*I) : RegInfo.createVirtualRegister(RC); in GetRegistersForValue()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 492 unsigned &AssignedReg = FuncInfo.ValueMap[I]; in updateValueMap() local
493 if (AssignedReg == 0) in updateValueMap()
495 AssignedReg = Reg; in updateValueMap()
496 else if (Reg != AssignedReg) { in updateValueMap()
499 FuncInfo.RegFixups[AssignedReg + i] = Reg + i; in updateValueMap()
503 AssignedReg = Reg; in updateValueMap()
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| D | SelectionDAGBuilder.cpp | 7959 unsigned AssignedReg; in GetRegistersForValue() local
7961 std::tie(AssignedReg, RC) = TLI.getRegForInlineAsmConstraint( in GetRegistersForValue()
8032 if (AssignedReg) { in GetRegistersForValue()
8033 for (; *I != AssignedReg; ++I) in GetRegistersForValue()
8039 Register R = AssignedReg ? Register(*I) : RegInfo.createVirtualRegister(RC); in GetRegistersForValue()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 11082 unsigned AssignedReg; in requiresUniformRegister() local
11084 std::tie(AssignedReg, RC) = getRegForInlineAsmConstraint( in requiresUniformRegister()
11088 if (AssignedReg != 0 && SIRI->isSGPRReg(MRI, AssignedReg)) in requiresUniformRegister()
|