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/external/llvm-project/llvm/test/Transforms/IndVarSimplify/X86/
Div-widen.ll20 ; CHECK: B18.preheader:
21 ; CHECK-NEXT: br label [[B18:%.*]]
22 ; CHECK: B18:
33 ; CHECK-NEXT: br i1 [[T2]], label [[B6_LOOPEXIT:%.*]], label [[B18]]
39 ; CHECK-NEXT: [[DOT02_LCSSA_WIDE:%.*]] = phi i64 [ [[INDVARS_IV]], [[B18]] ]
45 br i1 undef, label %B18, label %B6
47 B18: ; preds = %B24, %Prologue
57 B24: ; preds = %B18
59 br i1 %t2, label %B6, label %B18
64 exit24: ; preds = %B18
[all …]
/external/llvm/test/Transforms/IndVarSimplify/
Div-widen.ll11 ; CHECK-LABEL: B18:
22 br i1 undef, label %B18, label %B6
24 B18: ; preds = %B24, %Prologue
33 B24: ; preds = %B18
35 br i1 %t2, label %B6, label %B18
40 exit24: ; preds = %B18
/external/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h130 case AArch64::D18: return AArch64::B18; in getBRegFromDReg()
170 case AArch64::B18: return AArch64::D18; in getDRegFromBReg()
/external/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td234 def B18 : AArch64Reg<18, "b18">, DwarfRegNum<[82]>;
268 def H18 : AArch64Reg<18, "h18", [B18]>, DwarfRegAlias<B18>;
303 def S18 : AArch64Reg<18, "s18", [H18]>, DwarfRegAlias<B18>;
338 def D18 : AArch64Reg<18, "d18", [S18], ["v18", ""]>, DwarfRegAlias<B18>;
373 def Q18 : AArch64Reg<18, "q18", [D18], ["v18", ""]>, DwarfRegAlias<B18>;
/external/swiftshader/third_party/subzero/src/
DIceAssemblerARM32.cpp54 static constexpr IValueT B18 = 1 << 18; variable
1524 B21 | B20 | B19 | B18 | B17 | B16 | B15 | B14 | B13 | B12 | B6 | B4 | in dmb()
2144 constexpr IValueT RbitOpcode = B26 | B25 | B23 | B22 | B21 | B20 | B19 | B18 | in rbit()
2156 constexpr IValueT RevOpcode = B26 | B25 | B23 | B21 | B20 | B19 | B18 | B17 | in rev()
2548 constexpr IValueT VcmpdOpcode = B23 | B21 | B20 | B18 | B6; in vcmpd()
2556 constexpr IValueT VcmpdzOpcode = B23 | B21 | B20 | B18 | B16 | B6; in vcmpdz()
2567 constexpr IValueT VcmpsOpcode = B23 | B21 | B20 | B18 | B6; in vcmps()
2575 constexpr IValueT VcmpszOpcode = B23 | B21 | B20 | B18 | B16 | B6; in vcmpsz()
2628 B23 | B21 | B20 | B18 | B17 | B16 | B8 | B7 | B6; in vcvtsd()
2642 constexpr IValueT VcvtisOpcode = B23 | B21 | B20 | B19 | B18 | B16 | B7 | B6; in vcvtis()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h129 case AArch64::D18: return AArch64::B18; in getBRegFromDReg()
169 case AArch64::B18: return AArch64::D18; in getDRegFromBReg()
/external/llvm-project/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h129 case AArch64::D18: return AArch64::B18; in getBRegFromDReg()
169 case AArch64::B18: return AArch64::D18; in getDRegFromBReg()
/external/harfbuzz_ng/test/shaping/data/text-rendering-tests/tests/
DSHBALI-1.tests3 ….ttf:--font-size=1000 --ned --remove-default-ignorables --font-funcs=ft:U+1B18,U+1B3B:[gid28|gid62…
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td270 def B18 : AArch64Reg<18, "b18">, DwarfRegNum<[82]>;
304 def H18 : AArch64Reg<18, "h18", [B18]>, DwarfRegAlias<B18>;
339 def S18 : AArch64Reg<18, "s18", [H18]>, DwarfRegAlias<B18>;
374 def D18 : AArch64Reg<18, "d18", [S18], ["v18", ""]>, DwarfRegAlias<B18>;
409 def Q18 : AArch64Reg<18, "q18", [D18], ["v18", ""]>, DwarfRegAlias<B18>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td267 def B18 : AArch64Reg<18, "b18">, DwarfRegNum<[82]>;
301 def H18 : AArch64Reg<18, "h18", [B18]>, DwarfRegAlias<B18>;
336 def S18 : AArch64Reg<18, "s18", [H18]>, DwarfRegAlias<B18>;
371 def D18 : AArch64Reg<18, "d18", [S18], ["v18", ""]>, DwarfRegAlias<B18>;
406 def Q18 : AArch64Reg<18, "q18", [D18], ["v18", ""]>, DwarfRegAlias<B18>;
/external/swiftshader/third_party/subzero/src/DartARM32/
Dassembler_arm.cc1061 EmitVFPsd(cond, B23 | B21 | B20 | B18 | B17 | B16 | B8 | B7 | B6, sd, dm);
1066 EmitVFPds(cond, B23 | B21 | B20 | B18 | B17 | B16 | B7 | B6, dd, sm);
1071 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B16 | B7 | B6, sd, S0, sm);
1076 EmitVFPsd(cond, B23 | B21 | B20 | B19 | B18 | B16 | B8 | B7 | B6, sd, dm); in vcvtid()
1092 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B7 | B6, sd, S0, sm);
1097 EmitVFPsd(cond, B23 | B21 | B20 | B19 | B18 | B8 | B7 | B6, sd, dm);
1112 EmitVFPsss(cond, B23 | B21 | B20 | B18 | B6, sd, S0, sm);
1117 EmitVFPddd(cond, B23 | B21 | B20 | B18 | B6, dd, D0, dm);
1122 EmitVFPsss(cond, B23 | B21 | B20 | B18 | B16 | B6, sd, S0, S0);
1127 EmitVFPddd(cond, B23 | B21 | B20 | B18 | B16 | B6, dd, D0, D0);
Dassembler_arm.h61 B18 = 1 << 18,
/external/protobuf/python/google/protobuf/internal/
Dmore_messages.proto122 message B18 {} message
/external/OpenCSD/decoder/tests/snapshots/a55-test-tpiu/
Ddevice1.ini89 B18=0x00000000 key
/external/OpenCSD/decoder/tests/snapshots/a57_single_step/
Ddevice1.ini89 B18=0x00000000 key
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dand-or-icmps.ll243 %B18 = mul i16 %B23, %B7
250 %B29 = srem i16 %L4, %B18
/external/llvm-project/llvm/test/Transforms/SLPVectorizer/X86/
Darith-mul-umulo.ll334 ; CHECK-NEXT: [[B18:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
366 ; CHECK-NEXT: [[C18:%.*]] = call { i16, i1 } @llvm.umul.with.overflow.i16(i16 [[A18]], i16 [[B18…
693 ; CHECK-NEXT: [[B18:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
757 ; CHECK-NEXT: [[C18:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[A18]], i8 [[B18]])
Darith-add-uaddo.ll334 ; CHECK-NEXT: [[B18:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
366 ; CHECK-NEXT: [[C18:%.*]] = call { i16, i1 } @llvm.uadd.with.overflow.i16(i16 [[A18]], i16 [[B18…
693 ; CHECK-NEXT: [[B18:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
757 ; CHECK-NEXT: [[C18:%.*]] = call { i8, i1 } @llvm.uadd.with.overflow.i8(i8 [[A18]], i8 [[B18]])
Darith-mul-smulo.ll334 ; CHECK-NEXT: [[B18:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
366 ; CHECK-NEXT: [[C18:%.*]] = call { i16, i1 } @llvm.smul.with.overflow.i16(i16 [[A18]], i16 [[B18…
693 ; CHECK-NEXT: [[B18:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
757 ; CHECK-NEXT: [[C18:%.*]] = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 [[A18]], i8 [[B18]])
Darith-sub-usubo.ll334 ; CHECK-NEXT: [[B18:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
366 ; CHECK-NEXT: [[C18:%.*]] = call { i16, i1 } @llvm.usub.with.overflow.i16(i16 [[A18]], i16 [[B18…
693 ; CHECK-NEXT: [[B18:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
757 ; CHECK-NEXT: [[C18:%.*]] = call { i8, i1 } @llvm.usub.with.overflow.i8(i8 [[A18]], i8 [[B18]])
Darith-sub-ssubo.ll334 ; CHECK-NEXT: [[B18:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
366 ; CHECK-NEXT: [[C18:%.*]] = call { i16, i1 } @llvm.ssub.with.overflow.i16(i16 [[A18]], i16 [[B18…
693 ; CHECK-NEXT: [[B18:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
757 ; CHECK-NEXT: [[C18:%.*]] = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 [[A18]], i8 [[B18]])
Darith-add-saddo.ll334 ; CHECK-NEXT: [[B18:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
366 ; CHECK-NEXT: [[C18:%.*]] = call { i16, i1 } @llvm.sadd.with.overflow.i16(i16 [[A18]], i16 [[B18…
693 ; CHECK-NEXT: [[B18:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
757 ; CHECK-NEXT: [[C18:%.*]] = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 [[A18]], i8 [[B18]])
/external/icu/icu4c/source/data/unidata/norm2/
Dnfc.txt2014 2F871>21B18
/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp351 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp400 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19,

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