/external/swiftshader/third_party/subzero/src/ |
D | IceAssemblerARM32.cpp | 59 static constexpr IValueT B23 = 1 << 23; variable 1125 constexpr IValueT VmovssOpcode = B23 | B21 | B20 | B6; in emitMoveSS() 1261 B24 | B23 | B21 | B20 | B19 | B17 | B16 | B10 | B9 | Opcode; in emitSIMDCvtqq() 1653 IValueT Encoding = (Cond << kConditionShift) | B24 | B23 | B11 | B10 | B9 | in emitMemExOp() 2144 constexpr IValueT RbitOpcode = B26 | B25 | B23 | B22 | B21 | B20 | B19 | B18 | in rbit() 2156 constexpr IValueT RevOpcode = B26 | B25 | B23 | B21 | B20 | B19 | B18 | B17 | in rev() 2210 constexpr IValueT SxtOpcode = B26 | B25 | B23 | B21; in sxt() 2314 constexpr IValueT UmullOpcode = B23; in umull() 2322 constexpr IValueT UxtOpcode = B26 | B25 | B23 | B22 | B21; in uxt() 2336 constexpr IValueT VabssOpcode = B23 | B21 | B20 | B7 | B6; in vabss() [all …]
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/external/llvm-project/llvm/test/CodeGen/X86/ |
D | vbinop-simplify-bug.ll | 20 %B23 = sub <8 x i32> %Shuff, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1> 21 ret <8 x i32> %B23
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D | fold-vector-shuffle-crash.ll | 57 %B23 = sub i64 419346, %4 60 %Cmp26 = icmp ugt i64 %B, %B23 163 %I97 = insertelement <4 x i64> zeroinitializer, i64 %B23, i32 1 336 %Sl226 = select i1 %Cmp93, i64 %E28, i64 %B23
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/external/llvm/test/CodeGen/X86/ |
D | vbinop-simplify-bug.ll | 20 %B23 = sub <8 x i32> %Shuff, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1> 21 ret <8 x i32> %B23
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D | fold-vector-shuffle-crash.ll | 57 %B23 = sub i64 419346, %4 60 %Cmp26 = icmp ugt i64 %B, %B23 163 %I97 = insertelement <4 x i64> zeroinitializer, i64 %B23, i32 1 336 %Sl226 = select i1 %Cmp93, i64 %E28, i64 %B23
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/external/llvm-project/llvm/test/Transforms/SCCP/ |
D | latticeval-invalidate.ll | 19 %B23 = lshr i64 %B8, undef 28 %B15 = sub i64 %B8, %B23
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/external/swiftshader/third_party/subzero/src/DartARM32/ |
D | assembler_arm.cc | 397 EmitMulOp(cond, B23 | B22, rd_lo, rd_hi, rn, rm); in smull() 405 EmitMulOp(cond, B23, rd_lo, rd_hi, rn, rm); 412 EmitMulOp(cond, B23 | B21, rd_lo, rd_hi, rn, rm); in umlal() 545 B23 | 562 B23 | 881 EmitVFPsss(cond, B23 | B21 | B20 | B6, sd, S0, sm); 886 EmitVFPddd(cond, B23 | B21 | B20 | B6, dd, D0, dm); 900 EmitVFPsss(cond, B23 | B21 | B20 | ((imm8 >> 4)*B16) | (imm8 & 0xf), 918 EmitVFPddd(cond, B23 | B21 | B20 | ((imm8 >> 4)*B16) | B8 | (imm8 & 0xf), 988 EmitVFPsss(cond, B23, sd, sn, sm); [all …]
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/external/llvm/test/CodeGen/Mips/msa/ |
D | llvm-stress-s525530439.ll | 51 %B23 = shl i32 71140, 439732 63 %Sl31 = select i1 %Cmp18, i32 %3, i32 %B23 133 store i32 %B23, i32* %PC
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D | llvm-stress-s3861334421.ll | 53 %B23 = fdiv double %Sl17, 0.000000e+00 124 %B68 = frem double %B23, %Sl17
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/external/llvm-project/llvm/test/CodeGen/Mips/msa/ |
D | llvm-stress-s525530439.ll | 51 %B23 = shl i32 71140, 439732 63 %Sl31 = select i1 %Cmp18, i32 %3, i32 %B23 133 store i32 %B23, i32* %PC
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D | llvm-stress-s3861334421.ll | 53 %B23 = fdiv double %Sl17, 0.000000e+00 124 %B68 = frem double %B23, %Sl17
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/external/llvm/lib/Target/AArch64/Utils/ |
D | AArch64BaseInfo.h | 135 case AArch64::D23: return AArch64::B23; in getBRegFromDReg() 175 case AArch64::B23: return AArch64::D23; in getDRegFromBReg()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64RegisterInfo.td | 239 def B23 : AArch64Reg<23, "b23">, DwarfRegNum<[87]>; 273 def H23 : AArch64Reg<23, "h23", [B23]>, DwarfRegAlias<B23>; 308 def S23 : AArch64Reg<23, "s23", [H23]>, DwarfRegAlias<B23>; 343 def D23 : AArch64Reg<23, "d23", [S23], ["v23", ""]>, DwarfRegAlias<B23>; 378 def Q23 : AArch64Reg<23, "q23", [D23], ["v23", ""]>, DwarfRegAlias<B23>;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/ |
D | AArch64BaseInfo.h | 134 case AArch64::D23: return AArch64::B23; in getBRegFromDReg() 174 case AArch64::B23: return AArch64::D23; in getDRegFromBReg()
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/external/llvm-project/llvm/lib/Target/AArch64/Utils/ |
D | AArch64BaseInfo.h | 134 case AArch64::D23: return AArch64::B23; in getBRegFromDReg() 174 case AArch64::B23: return AArch64::D23; in getDRegFromBReg()
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/external/llvm-project/clang/test/Misc/ |
D | diag-template-diffing.cpp | 591 typedef const C23<int> B23; typedef 592 template<class ...T> using A23 = B23;
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/external/clang/test/Misc/ |
D | diag-template-diffing.cpp | 591 typedef const C23<int> B23; typedef 592 template<class ...T> using A23 = B23;
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/external/llvm-project/llvm/lib/Target/AArch64/ |
D | AArch64RegisterInfo.td | 275 def B23 : AArch64Reg<23, "b23">, DwarfRegNum<[87]>; 309 def H23 : AArch64Reg<23, "h23", [B23]>, DwarfRegAlias<B23>; 344 def S23 : AArch64Reg<23, "s23", [H23]>, DwarfRegAlias<B23>; 379 def D23 : AArch64Reg<23, "d23", [S23], ["v23", ""]>, DwarfRegAlias<B23>; 414 def Q23 : AArch64Reg<23, "q23", [D23], ["v23", ""]>, DwarfRegAlias<B23>;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64RegisterInfo.td | 272 def B23 : AArch64Reg<23, "b23">, DwarfRegNum<[87]>; 306 def H23 : AArch64Reg<23, "h23", [B23]>, DwarfRegAlias<B23>; 341 def S23 : AArch64Reg<23, "s23", [H23]>, DwarfRegAlias<B23>; 376 def D23 : AArch64Reg<23, "d23", [S23], ["v23", ""]>, DwarfRegAlias<B23>; 411 def Q23 : AArch64Reg<23, "q23", [D23], ["v23", ""]>, DwarfRegAlias<B23>;
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/external/protobuf/python/google/protobuf/internal/ |
D | more_messages.proto | 127 message B23 {} message
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/external/OpenCSD/decoder/tests/snapshots/a55-test-tpiu/ |
D | device1.ini | 94 B23=0x00000000 key
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/external/OpenCSD/decoder/tests/snapshots/a57_single_step/ |
D | device1.ini | 94 B23=0x00000000 key
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/external/llvm-project/llvm/test/Transforms/InstCombine/ |
D | and-or-icmps.ll | 239 %B23 = mul i16 %B11, %B11 243 %B18 = mul i16 %B23, %B7
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/external/llvm-project/llvm/test/CodeGen/ARM/ParallelDSP/ |
D | unroll-n-jam-smlad.ll | 189 %B23 = load i16, i16* %arrayidx4.us.i.1.3.i, align 2 190 %conv.us.i.1.3.i = sext i16 %B23 to i32
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/external/llvm-project/llvm/test/Transforms/VectorCombine/X86/ |
D | extract-binop.ll | 464 ; CHECK-NEXT: [[B23:%.*]] = extractelement <4 x float> [[TMP3]], i64 3 467 ; CHECK-NEXT: [[V3:%.*]] = insertelement <4 x float> [[V2]], float [[B23]], i32 3
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