Home
last modified time | relevance | path

Searched refs:B24 (Results 1 – 25 of 60) sorted by relevance

123

/external/llvm-project/llvm/tools/msbuild/
Dllvm.sln6 Project("{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC}") = "llvm", "llvm.csproj", "{62530D9E-1B24-4C31-8DC…
14 {62530D9E-1B24-4C31-8DC9-AE47E9E5DC53}.Debug|Any CPU.ActiveCfg = Debug|Any CPU
15 {62530D9E-1B24-4C31-8DC9-AE47E9E5DC53}.Debug|Any CPU.Build.0 = Debug|Any CPU
16 {62530D9E-1B24-4C31-8DC9-AE47E9E5DC53}.Release|Any CPU.ActiveCfg = Release|Any CPU
17 {62530D9E-1B24-4C31-8DC9-AE47E9E5DC53}.Release|Any CPU.Build.0 = Release|Any CPU
/external/llvm-project/llvm/test/Transforms/IndVarSimplify/X86/
Div-widen.ll23 … [[INDVARS_IV:%.*]] = phi i64 [ 0, [[B18_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[B24:%.*]] ]
30 ; CHECK-NEXT: br i1 [[T]], label [[EXIT24:%.*]], label [[B24]]
31 ; CHECK: B24:
47 B18: ; preds = %B24, %Prologue
48 %.02 = phi i32 [ 0, %Prologue ], [ %tmp33, %B24 ]
55 br i1 %t, label %exit24, label %B24
57 B24: ; preds = %B18
77 ; CHECK-NEXT: [[DOT02:%.*]] = phi i32 [ [[TMP33:%.*]], [[B24:%.*]] ], [ 0, [[B18_PREHEADER]] ]
82 ; CHECK-NEXT: br i1 [[T]], label [[EXIT24:%.*]], label [[B24]]
83 ; CHECK: B24:
[all …]
/external/llvm/test/Transforms/IndVarSimplify/
Div-widen.ll24 B18: ; preds = %B24, %Prologue
25 %.02 = phi i32 [ 0, %Prologue ], [ %tmp33, %B24 ]
31 br i1 %t, label %exit24, label %B24
33 B24: ; preds = %B18
/external/swiftshader/third_party/subzero/src/
DIceAssemblerARM32.cpp60 static constexpr IValueT B24 = 1 << 24; variable
1071 B25 | B24 | B20 | B15 | B14 | B13 | B12 | B4 | in emitDivOp()
1261 B24 | B23 | B21 | B20 | B19 | B17 | B16 | B10 | B9 | Opcode; in emitSIMDCvtqq()
1392 const IValueT Encoding = (CondARM32::AL << kConditionShift) | B24 | B21 | in bkpt()
1440 int32_t Encoding = (encodeCondition(Cond) << kConditionShift) | B24 | B21 | in blx()
1451 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B24 | in bx()
1474 B24 | B22 | B21 | (0xF << 16) | (0xf << 8) | B4; in clz()
1523 (encodeCondition(CondARM32::kNone) << kConditionShift) | B26 | B24 | B22 | in dmb()
1653 IValueT Encoding = (Cond << kConditionShift) | B24 | B23 | B11 | B10 | B9 | in emitMemExOp()
1778 IValueT Opcode = B25 | B24 | (IsMovW ? 0 : B22); in emitMovwt()
[all …]
/external/swiftshader/third_party/subzero/src/DartARM32/
Dassembler_arm.cc315 B24 | B22 | B21 | (0xf << 16) |
325 B25 | B24 | ((imm16 >> 12) << 16) |
335 B25 | B24 | B22 | ((imm16 >> 12) << 16) |
446 B26 | B25 | B24 | B20 | B4 |
544 B24 |
561 B24 |
573 int32_t encoding = (kSpecialCondition << kConditionShift) | B26 | B24 | B22 | in clrex()
583 B25 | B24 | B21 | (0xf << 12);
729 B27 | B26 | B24 | B20 |
743 B27 | B26 | B24 |
[all …]
Dassembler_arm.h67 B24 = 1 << 24,
597 return (AL << kConditionShift) | B24 | B21 |
/external/python/cpython2/PCbuild/
Dpcbuild.sln62 Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "ssleay", "ssleay.vcxproj", "{10615B24-73BF-4EF…
516 {10615B24-73BF-4EFA-93AA-236916321317}.Debug|Win32.ActiveCfg = Debug|Win32
517 {10615B24-73BF-4EFA-93AA-236916321317}.Debug|Win32.Build.0 = Debug|Win32
518 {10615B24-73BF-4EFA-93AA-236916321317}.Debug|x64.ActiveCfg = Debug|x64
519 {10615B24-73BF-4EFA-93AA-236916321317}.Debug|x64.Build.0 = Debug|x64
520 {10615B24-73BF-4EFA-93AA-236916321317}.PGInstrument|Win32.ActiveCfg = Release|Win32
521 {10615B24-73BF-4EFA-93AA-236916321317}.PGInstrument|Win32.Build.0 = Release|Win32
522 {10615B24-73BF-4EFA-93AA-236916321317}.PGInstrument|x64.ActiveCfg = Release|x64
523 {10615B24-73BF-4EFA-93AA-236916321317}.PGInstrument|x64.Build.0 = Release|x64
524 {10615B24-73BF-4EFA-93AA-236916321317}.PGUpdate|Win32.ActiveCfg = Release|Win32
[all …]
/external/crosvm/devices/src/usb/xhci/
Dxhci_abi.rs559 trb_transfer_length: B24,
575 command_completion_parameter: B24,
587 reserved0: B24,
590 reserved2: B24,
/external/llvm-project/llvm/test/TableGen/
Dforeach-multiclass.td24 // CHECK: def B24 {
/external/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h136 case AArch64::D24: return AArch64::B24; in getBRegFromDReg()
176 case AArch64::B24: return AArch64::D24; in getDRegFromBReg()
/external/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td240 def B24 : AArch64Reg<24, "b24">, DwarfRegNum<[88]>;
274 def H24 : AArch64Reg<24, "h24", [B24]>, DwarfRegAlias<B24>;
309 def S24 : AArch64Reg<24, "s24", [H24]>, DwarfRegAlias<B24>;
344 def D24 : AArch64Reg<24, "d24", [S24], ["v24", ""]>, DwarfRegAlias<B24>;
379 def Q24 : AArch64Reg<24, "q24", [D24], ["v24", ""]>, DwarfRegAlias<B24>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h135 case AArch64::D24: return AArch64::B24; in getBRegFromDReg()
175 case AArch64::B24: return AArch64::D24; in getDRegFromBReg()
/external/llvm-project/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h135 case AArch64::D24: return AArch64::B24; in getBRegFromDReg()
175 case AArch64::B24: return AArch64::D24; in getDRegFromBReg()
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td276 def B24 : AArch64Reg<24, "b24">, DwarfRegNum<[88]>;
310 def H24 : AArch64Reg<24, "h24", [B24]>, DwarfRegAlias<B24>;
345 def S24 : AArch64Reg<24, "s24", [H24]>, DwarfRegAlias<B24>;
380 def D24 : AArch64Reg<24, "d24", [S24], ["v24", ""]>, DwarfRegAlias<B24>;
415 def Q24 : AArch64Reg<24, "q24", [D24], ["v24", ""]>, DwarfRegAlias<B24>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td273 def B24 : AArch64Reg<24, "b24">, DwarfRegNum<[88]>;
307 def H24 : AArch64Reg<24, "h24", [B24]>, DwarfRegAlias<B24>;
342 def S24 : AArch64Reg<24, "s24", [H24]>, DwarfRegAlias<B24>;
377 def D24 : AArch64Reg<24, "d24", [S24], ["v24", ""]>, DwarfRegAlias<B24>;
412 def Q24 : AArch64Reg<24, "q24", [D24], ["v24", ""]>, DwarfRegAlias<B24>;
/external/protobuf/python/google/protobuf/internal/
Dmore_messages.proto128 message B24 {} message
/external/OpenCSD/decoder/tests/snapshots/a55-test-tpiu/
Ddevice1.ini95 B24=0x00000000 key
/external/OpenCSD/decoder/tests/snapshots/a57_single_step/
Ddevice1.ini95 B24=0x00000000 key
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dshift.ll1764 %B24 = ashr i177 %L7, %B6
1766 %C17 = icmp sgt i177 %B36, %B24
1768 %B28 = urem i177 %B24, %B6
1792 %B24 = ashr i177 %L, %B6
1793 %C17 = icmp sgt i177 %B, %B24
1795 %B28 = urem i177 %B24, %B6
/external/llvm-project/llvm/test/Transforms/SLPVectorizer/X86/
Darith-mul-umulo.ll340 ; CHECK-NEXT: [[B24:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
372 ; CHECK-NEXT: [[C24:%.*]] = call { i16, i1 } @llvm.umul.with.overflow.i16(i16 [[A24]], i16 [[B24…
699 ; CHECK-NEXT: [[B24:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
763 ; CHECK-NEXT: [[C24:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[A24]], i8 [[B24]])
Darith-add-uaddo.ll340 ; CHECK-NEXT: [[B24:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
372 ; CHECK-NEXT: [[C24:%.*]] = call { i16, i1 } @llvm.uadd.with.overflow.i16(i16 [[A24]], i16 [[B24…
699 ; CHECK-NEXT: [[B24:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
763 ; CHECK-NEXT: [[C24:%.*]] = call { i8, i1 } @llvm.uadd.with.overflow.i8(i8 [[A24]], i8 [[B24]])
Darith-mul-smulo.ll340 ; CHECK-NEXT: [[B24:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
372 ; CHECK-NEXT: [[C24:%.*]] = call { i16, i1 } @llvm.smul.with.overflow.i16(i16 [[A24]], i16 [[B24…
699 ; CHECK-NEXT: [[B24:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
763 ; CHECK-NEXT: [[C24:%.*]] = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 [[A24]], i8 [[B24]])
Darith-sub-usubo.ll340 ; CHECK-NEXT: [[B24:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
372 ; CHECK-NEXT: [[C24:%.*]] = call { i16, i1 } @llvm.usub.with.overflow.i16(i16 [[A24]], i16 [[B24…
699 ; CHECK-NEXT: [[B24:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
763 ; CHECK-NEXT: [[C24:%.*]] = call { i8, i1 } @llvm.usub.with.overflow.i8(i8 [[A24]], i8 [[B24]])
Darith-sub-ssubo.ll340 ; CHECK-NEXT: [[B24:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
372 ; CHECK-NEXT: [[C24:%.*]] = call { i16, i1 } @llvm.ssub.with.overflow.i16(i16 [[A24]], i16 [[B24…
699 ; CHECK-NEXT: [[B24:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
763 ; CHECK-NEXT: [[C24:%.*]] = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 [[A24]], i8 [[B24]])
Darith-add-saddo.ll340 ; CHECK-NEXT: [[B24:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
372 ; CHECK-NEXT: [[C24:%.*]] = call { i16, i1 } @llvm.sadd.with.overflow.i16(i16 [[A24]], i16 [[B24…
699 ; CHECK-NEXT: [[B24:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
763 ; CHECK-NEXT: [[C24:%.*]] = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 [[A24]], i8 [[B24]])

123