Home
last modified time | relevance | path

Searched refs:B26 (Results 1 – 25 of 58) sorted by relevance

123

/external/llvm/test/CodeGen/AArch64/
Darm64-2013-01-23-frem-crash.ll6 %B26 = frem float 0.000000e+00, undef
10 store float %B26, float* undef
/external/llvm-project/llvm/test/CodeGen/AArch64/
Darm64-2013-01-23-frem-crash.ll6 %B26 = frem float 0.000000e+00, undef
10 store float %B26, float* undef
/external/llvm-project/llvm/test/CodeGen/X86/
Dpr10524.ll8 %B26 = sub <2 x i32> %Shuff22, zeroinitializer
9 %S79 = icmp eq <2 x i32> %B26, zeroinitializer
/external/llvm/test/CodeGen/X86/
Dpr10524.ll8 %B26 = sub <2 x i32> %Shuff22, zeroinitializer
9 %S79 = icmp eq <2 x i32> %B26, zeroinitializer
/external/swiftshader/third_party/subzero/src/
DIceAssemblerARM32.cpp62 static constexpr IValueT B26 = 1 << 26; variable
1070 (Rn << kDivRnShift) | (Rd << kDivRdShift) | B26 | in emitDivOp()
1111 const IValueT Encoding = B27 | B26 | B25 | B11 | B9 | B8 | B4 | in emitInsertExtractInt()
1277 constexpr IValueT VFPOpcode = B27 | B26 | B25 | B11 | B9 | B8; in emitVFPddd()
1301 constexpr IValueT VFPOpcode = B27 | B26 | B25 | B11 | B9; in emitVFPsss()
1523 (encodeCondition(CondARM32::kNone) << kConditionShift) | B26 | B24 | B22 | in dmb()
2144 constexpr IValueT RbitOpcode = B26 | B25 | B23 | B22 | B21 | B20 | B19 | B18 | in rbit()
2156 constexpr IValueT RevOpcode = B26 | B25 | B23 | B21 | B20 | B19 | B18 | B17 | in rev()
2210 constexpr IValueT SxtOpcode = B26 | B25 | B23 | B21; in sxt()
2322 constexpr IValueT UxtOpcode = B26 | B25 | B23 | B22 | B21; in uxt()
[all …]
/external/swiftshader/third_party/subzero/src/DartARM32/
Dassembler_arm.cc113 B26 | (ad.kind() == Address::Immediate ? 0 : B25) |
446 B26 | B25 | B24 | B20 | B4 |
573 int32_t encoding = (kSpecialCondition << kConditionShift) | B26 | B24 | B22 | in clrex()
596 B27 | B26 | B25 |
612 B27 | B26 | B25 | B20 |
633 B26 | B22 | (static_cast<int32_t>(rt2) * B16) | in vmovsrr()
654 B26 | B22 | B20 | (static_cast<int32_t>(rt2) * B16) | in vmovrrs()
672 B27 | B26 | B25 |
693 B27 | B26 | B22 |
715 B27 | B26 | B22 | B20 |
[all …]
Dassembler_arm.h69 B26 = 1 << 26,
/external/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h138 case AArch64::D26: return AArch64::B26; in getBRegFromDReg()
178 case AArch64::B26: return AArch64::D26; in getDRegFromBReg()
/external/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td242 def B26 : AArch64Reg<26, "b26">, DwarfRegNum<[90]>;
276 def H26 : AArch64Reg<26, "h26", [B26]>, DwarfRegAlias<B26>;
311 def S26 : AArch64Reg<26, "s26", [H26]>, DwarfRegAlias<B26>;
346 def D26 : AArch64Reg<26, "d26", [S26], ["v26", ""]>, DwarfRegAlias<B26>;
381 def Q26 : AArch64Reg<26, "q26", [D26], ["v26", ""]>, DwarfRegAlias<B26>;
/external/llvm-project/llvm/test/MC/COFF/
Dcv-inline-linetable.s76 # PDB-NEXT: 0B26 code 0x1F (+0x6) line 2 (+1)
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h137 case AArch64::D26: return AArch64::B26; in getBRegFromDReg()
177 case AArch64::B26: return AArch64::D26; in getDRegFromBReg()
/external/llvm-project/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h137 case AArch64::D26: return AArch64::B26; in getBRegFromDReg()
177 case AArch64::B26: return AArch64::D26; in getDRegFromBReg()
/external/harfbuzz_ng/test/shaping/data/text-rendering-tests/tests/
DSHBALI-1.tests9 …ze=1000 --ned --remove-default-ignorables --font-funcs=ft:U+1B13,U+1B44,U+1B26,U+1B03:[gid23|gid14…
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td278 def B26 : AArch64Reg<26, "b26">, DwarfRegNum<[90]>;
312 def H26 : AArch64Reg<26, "h26", [B26]>, DwarfRegAlias<B26>;
347 def S26 : AArch64Reg<26, "s26", [H26]>, DwarfRegAlias<B26>;
382 def D26 : AArch64Reg<26, "d26", [S26], ["v26", ""]>, DwarfRegAlias<B26>;
417 def Q26 : AArch64Reg<26, "q26", [D26], ["v26", ""]>, DwarfRegAlias<B26>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td275 def B26 : AArch64Reg<26, "b26">, DwarfRegNum<[90]>;
309 def H26 : AArch64Reg<26, "h26", [B26]>, DwarfRegAlias<B26>;
344 def S26 : AArch64Reg<26, "s26", [H26]>, DwarfRegAlias<B26>;
379 def D26 : AArch64Reg<26, "d26", [S26], ["v26", ""]>, DwarfRegAlias<B26>;
414 def Q26 : AArch64Reg<26, "q26", [D26], ["v26", ""]>, DwarfRegAlias<B26>;
/external/llvm-project/llvm/test/tools/dsymutil/ARM/
Dobfuscated.test20 RUN: cp %p/../Inputs/obfuscated.map %t.mapdir/506AA50A-6B26-3B37-86D2-DC6EBD57B720.bcsymbolmap
/external/protobuf/python/google/protobuf/internal/
Dmore_messages.proto130 message B26 {} message
/external/OpenCSD/decoder/tests/snapshots/a55-test-tpiu/
Ddevice1.ini97 B26=0x00000000 key
/external/OpenCSD/decoder/tests/snapshots/a57_single_step/
Ddevice1.ini97 B26=0x00000000 key
/external/llvm-project/llvm/test/Transforms/SLPVectorizer/X86/
Darith-mul-umulo.ll342 ; CHECK-NEXT: [[B26:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
374 ; CHECK-NEXT: [[C26:%.*]] = call { i16, i1 } @llvm.umul.with.overflow.i16(i16 [[A26]], i16 [[B26…
701 ; CHECK-NEXT: [[B26:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
765 ; CHECK-NEXT: [[C26:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[A26]], i8 [[B26]])
Darith-add-uaddo.ll342 ; CHECK-NEXT: [[B26:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
374 ; CHECK-NEXT: [[C26:%.*]] = call { i16, i1 } @llvm.uadd.with.overflow.i16(i16 [[A26]], i16 [[B26…
701 ; CHECK-NEXT: [[B26:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
765 ; CHECK-NEXT: [[C26:%.*]] = call { i8, i1 } @llvm.uadd.with.overflow.i8(i8 [[A26]], i8 [[B26]])
Darith-mul-smulo.ll342 ; CHECK-NEXT: [[B26:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
374 ; CHECK-NEXT: [[C26:%.*]] = call { i16, i1 } @llvm.smul.with.overflow.i16(i16 [[A26]], i16 [[B26…
701 ; CHECK-NEXT: [[B26:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
765 ; CHECK-NEXT: [[C26:%.*]] = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 [[A26]], i8 [[B26]])
Darith-sub-usubo.ll342 ; CHECK-NEXT: [[B26:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
374 ; CHECK-NEXT: [[C26:%.*]] = call { i16, i1 } @llvm.usub.with.overflow.i16(i16 [[A26]], i16 [[B26…
701 ; CHECK-NEXT: [[B26:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
765 ; CHECK-NEXT: [[C26:%.*]] = call { i8, i1 } @llvm.usub.with.overflow.i8(i8 [[A26]], i8 [[B26]])
Darith-sub-ssubo.ll342 ; CHECK-NEXT: [[B26:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
374 ; CHECK-NEXT: [[C26:%.*]] = call { i16, i1 } @llvm.ssub.with.overflow.i16(i16 [[A26]], i16 [[B26…
701 ; CHECK-NEXT: [[B26:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
765 ; CHECK-NEXT: [[C26:%.*]] = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 [[A26]], i8 [[B26]])
Darith-add-saddo.ll342 ; CHECK-NEXT: [[B26:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
374 ; CHECK-NEXT: [[C26:%.*]] = call { i16, i1 } @llvm.sadd.with.overflow.i16(i16 [[A26]], i16 [[B26…
701 ; CHECK-NEXT: [[B26:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
765 ; CHECK-NEXT: [[C26:%.*]] = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 [[A26]], i8 [[B26]])

123