Searched refs:BASE1 (Results 1 – 14 of 14) sorted by relevance
| /external/llvm/test/CodeGen/ARM/ |
| D | static-addr-hoisting.ll | 5 ; CHECK: movw r[[BASE1:[0-9]+]], #16960
7 ; CHECK: movt r[[BASE1]], #15
9 ; CHECK: str [[VAL]], [r[[BASE1]]]
10 ; CHECK: str [[VAL]], [r[[BASE1]], #24]
11 ; CHECK: str.w [[VAL]], [r[[BASE1]], #42]
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| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | static-addr-hoisting.ll | 5 ; CHECK: movw r[[BASE1:[0-9]+]], #16960
7 ; CHECK: movt r[[BASE1]], #15
9 ; CHECK-DAG: str [[VAL]], [r[[BASE1]]]
10 ; CHECK-DAG: str [[VAL]], [r[[BASE1]], #24]
11 ; CHECK-DAG: str.w [[VAL]], [r[[BASE1]], #42]
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| /external/clang/test/SemaCXX/ |
| D | decl-init-ref.cpp | 9 struct BASE1 { struct
13 class B : public BASE , public BASE1
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| D | ambig-user-defined-conversions.cpp | 7 struct BASE1 { struct
11 struct B : public BASE, BASE1 {};
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| /external/llvm-project/clang/test/SemaCXX/ |
| D | decl-init-ref.cpp | 9 struct BASE1 { struct
13 class B : public BASE , public BASE1
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| D | ambig-user-defined-conversions.cpp | 7 struct BASE1 { struct
11 struct B : public BASE, BASE1 {};
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| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | sve-calling-convention-byref.ll | 35 ; CHECK-DAG: [[BASE1:%[0-9]+]]:gpr64sp = ADDXri %stack.0, 0
36 ; CHECK-DAG: $x0 = COPY [[BASE1]]
69 ; CHECK-DAG: [[BASE1:%[0-9]+]]:gpr64sp = ADDXri %stack.0, 0
71 ; CHECK-DAG: $x0 = COPY [[BASE1]]
113 ; CHECK-DAG: [[BASE1:%[0-9]+]]:gpr64common = ADDXri %stack.0, 0
116 ; CHECK-DAG: STRXui killed [[BASE1]], [[SP]], 0
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| /external/llvm-project/llvm/test/Transforms/RewriteStatepointsForGC/ |
| D | rematerialize-derived-pointers.ll | 370 ; CHECK-NEXT: [[BASE1:%.*]] = call i32 addrspace(1)* @new_instance()
378 ; CHECK-NEXT: [[BASEPHI_BASE:%.*]] = phi i32 addrspace(1)* [ [[BASE1]], [[HERE]] ], [ [[BASE2]],…
379 ; CHECK-NEXT: [[BASEPHI:%.*]] = phi i32 addrspace(1)* [ [[BASE1]], [[HERE]] ], [ [[BASE2]], [[TH…
414 ; CHECK-NEXT: [[BASE1:%.*]] = call i32 addrspace(1)* @new_instance()
422 ; CHECK-NEXT: [[BASEPHI_BASE:%.*]] = phi i32 addrspace(1)* [ [[BASE1]], [[HERE]] ], [ [[BASE2]],…
423 ; CHECK-NEXT: [[BASEPHI:%.*]] = phi i32 addrspace(1)* [ [[BASE1]], [[HERE]] ], [ [[BASE2]], [[TH…
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| D | scalar-base-vector.ll | 17 ; CHECK-NEXT: [[PHI_BASE:%.*]] = phi i8 addrspace(1)* [ [[BASE1:%.*]], [[ENTRY:%.*]] ], [ [[BASE…
18 ; CHECK-NEXT: [[PHI:%.*]] = phi i8 addrspace(1)* [ [[BASE1]], [[ENTRY]] ], [ [[BASE21]], [[FIRST…
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| /external/llvm/test/CodeGen/X86/ |
| D | codegen-prepare-addrmode-sext.ll | 312 ; CHECK: [[BASE1:%[a-zA-Z_0-9-]+]] = add i64 [[SEXTADD]], 48
313 ; CHECK: [[ADDR1:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[BASE1]] to i32*
327 ; CHECK-GEP: [[BASE1:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[SEXTADD]] to i32*
328 ; CHECK-GEP: [[BCC1:%[a-zA-Z_0-9-]+]] = bitcast i32* [[BASE1]] to i8*
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | ds_write2.ll | 361 ; SI-DAG: v_mov_b32_e32 [[BASE1:v[0-9]+]], 0x4000{{$}}
363 ; SI-DAG: ds_write2_b32 [[BASE1]], v{{[0-9]+}}, v{{[0-9]+}} offset1:1
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| D | ds_read2.ll | 425 ; SI-DAG: v_mov_b32_e32 [[BASE1:v[0-9]+]], 0x4000
427 ; SI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASE1]] offset1:1
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| /external/llvm-project/llvm/test/Transforms/LoopIdiom/ |
| D | basic.ll | 47 ; CHECK-NEXT: [[BASE1:%.*]] = bitcast i16* [[BASE:%.*]] to i8*
49 ; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 2 [[BASE1]], i8 0, i64 [[TMP0]], i1 fals…
114 ; CHECK-NEXT: [[BASE1:%.*]] = bitcast i32* [[BASE:%.*]] to i8*
119 ; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 4 [[BASE1]], i8 1, i64 [[TMP0]], i1 fals…
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| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | codegen-prepare-addrmode-sext.ll | 311 ; CHECK: [[BASE1:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[SEXTADD]] to i32*
312 ; CHECK: [[BCC1:%[a-zA-Z_0-9-]+]] = bitcast i32* [[BASE1]] to i8*
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