Home
last modified time | relevance | path

Searched refs:BASE_SUB_SLOT_NUM (Results 1 – 4 of 4) sorted by relevance

/external/arm-trusted-firmware/drivers/renesas/rcar/qos/
Dqos_common.h17 ((126 * BASE_SUB_SLOT_NUM * 1000U) / 400)
20 ((252 * BASE_SUB_SLOT_NUM * 1000U) / 400)
45 ((SUB_SLOT_CYCLE_M3N * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
58 ((SUB_SLOT_CYCLE_H3_20 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
64 ((SUB_SLOT_CYCLE_H3_30 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
78 ((SUB_SLOT_CYCLE_H3N * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
95 ((SUB_SLOT_CYCLE_M3_11 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
97 ((SUB_SLOT_CYCLE_M3_30 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
101 #define BASE_SUB_SLOT_NUM 0x6U macro
105 ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
[all …]
/external/arm-trusted-firmware/drivers/renesas/rzg/qos/
Dqos_common.h16 ((126U * BASE_SUB_SLOT_NUM * 1000U) / 400U)
19 ((252U * BASE_SUB_SLOT_NUM * 1000U) / 400U)
35 ((SUB_SLOT_CYCLE_G2M_11 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
37 ((SUB_SLOT_CYCLE_G2M_30 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
41 #define BASE_SUB_SLOT_NUM 0x6U macro
45 ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
48 #define SL_INIT_SLOTSSLOT ((BASE_SUB_SLOT_NUM - 1U) << 16U)
/external/arm-trusted-firmware/drivers/renesas/rzg/ddr/ddr_b/
Dboot_init_dram.c117 #define BASE_SUB_SLOT_NUM (0x6U) macro
120 ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / \
/external/arm-trusted-firmware/drivers/renesas/rcar/ddr/ddr_b/
Dboot_init_dram.c129 #define BASE_SUB_SLOT_NUM (0x6U) macro
132 ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / \