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Searched refs:BC1EQZ (Results 1 – 18 of 18) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/Mips/longbranch/
Dbranch-limits-fp-mipsr6.mir125 BC1EQZ killed $d0_64, %bb.2, implicit-def $at
176 ; R6: BC1EQZ $d0_64, %bb.2 {
195 ; PIC: BC1EQZ $d0_64, %bb.3 {
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp529 case Mips::BC1EQZ: return Mips::BC1NEZ; in getOppositeBranchOpc()
530 case Mips::BC1NEZ: return Mips::BC1EQZ; in getOppositeBranchOpc()
DMipsInstrInfo.cpp336 case Mips::BC1EQZ: in isBranchOffsetInRange()
DMips32r6InstrInfo.td870 def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6, HARDFLOAT;
DMipsScheduleGeneric.td904 def : InstRW<[GenericWriteFPUCmp], (instrs BC1EQZ, BC1NEZ, SEL_D, SEL_S)>;
/external/llvm-project/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp543 case Mips::BC1EQZ: return Mips::BC1NEZ; in getOppositeBranchOpc()
544 case Mips::BC1NEZ: return Mips::BC1EQZ; in getOppositeBranchOpc()
DMipsInstrInfo.cpp337 case Mips::BC1EQZ: in isBranchOffsetInRange()
DMips32r6InstrInfo.td870 def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6, HARDFLOAT;
DMipsScheduleGeneric.td907 def : InstRW<[GenericWriteFPUCmp], (instrs BC1EQZ, BC1NEZ, SEL_D, SEL_S)>;
/external/pcre/dist2/src/sljit/
DsljitNativeMIPS_common.c139 #define BC1EQZ (HI(17) | (9 << 21) | FT(TMP_FREG3)) macro
1819 inst = BC1EQZ; \
/external/llvm/lib/Target/Mips/
DMips32r6InstrInfo.td751 def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6, HARDFLOAT;
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc197 25733U, // BC1EQZ
1986 0U, // BC1EQZ
DMipsGenDisassemblerTables.inc3965 /* 585 */ MCD_OPC_Decode, 180, 1, 229, 1, // Opcode: BC1EQZ
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenMCCodeEmitter.inc786 UINT64_C(1159725056), // BC1EQZ
3808 case Mips::BC1EQZ:
10248 CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1EQZ = 773
DMipsGenAsmWriter.inc2014 26524U, // BC1EQZ
4768 0U, // BC1EQZ
DMipsGenInstrInfo.inc788 BC1EQZ = 773,
5634 …deledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr }, // Inst #773 = BC1EQZ
DMipsGenDisassemblerTables.inc6390 /* 744 */ MCD::OPC_Decode, 133, 6, 215, 2, // Opcode: BC1EQZ
DMipsGenAsmMatcher.inc5636 …{ 796 /* bc1eqz */, Mips::BC1EQZ, Convert__FGR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips3…