| /external/llvm-project/llvm/test/CodeGen/Mips/longbranch/ |
| D | branch-limits-fp-mips.mir | 127 BC1T killed $fcc0, %bb.2, implicit-def $at
178 ; MIPS: BC1T $fcc0, %bb.2, implicit-def $at {
199 ; PIC: BC1T $fcc0, %bb.3, implicit-def $at {
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsInstPrinter.cpp | 242 case Mips::BC1T: in printAlias()
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| /external/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsInstPrinter.cpp | 242 case Mips::BC1T: in printAlias()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 422 case Mips::BC1T: return Mips::BC1F; in getOppositeBranchOpc()
423 case Mips::BC1F: return Mips::BC1T; in getOppositeBranchOpc()
513 Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B || in getAnalyzableBrOpc()
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| D | MipsInstrFPU.td | 532 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>,
593 def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>,
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| D | MipsISelLowering.cpp | 1095 return emitPseudoSELECT(MI, BB, true, Mips::BC1T); in EmitInstrWithCustomInserter()
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| /external/llvm/lib/Target/Mips/InstPrinter/ |
| D | MipsInstPrinter.cpp | 247 case Mips::BC1T: in printAlias()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 509 case Mips::BC1T: return Mips::BC1F; in getOppositeBranchOpc()
510 case Mips::BC1F: return Mips::BC1T; in getOppositeBranchOpc()
650 Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T || in getAnalyzableBrOpc()
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| D | MipsInstrInfo.cpp | 287 case Mips::BC1T: in isBranchOffsetInRange()
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| D | MipsInstrFPU.td | 701 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>,
896 defm : BC1_ALIASES<BC1T, "bc1t", BC1F, "bc1f">, ISA_MIPS1_NOT_32R6_64R6,
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| D | MipsScheduleP5600.td | 572 def : InstRW<[P5600WriteMoveFPUToGPR], (instrs BC1F, BC1FL, BC1T, BC1TL, CFC1,
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| D | MipsScheduleGeneric.td | 800 BC1T, BC1FL, BC1TL)>;
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| D | MipsISelLowering.cpp | 1450 return emitPseudoSELECT(MI, BB, true, Mips::BC1T); in EmitInstrWithCustomInserter()
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 523 case Mips::BC1T: return Mips::BC1F; in getOppositeBranchOpc()
524 case Mips::BC1F: return Mips::BC1T; in getOppositeBranchOpc()
664 Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T || in getAnalyzableBrOpc()
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| D | MipsInstrInfo.cpp | 288 case Mips::BC1T: in isBranchOffsetInRange()
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| D | MipsInstrFPU.td | 734 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>,
929 defm : BC1_ALIASES<BC1T, "bc1t", BC1F, "bc1f">, ISA_MIPS1_NOT_32R6_64R6,
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| D | MipsScheduleP5600.td | 573 def : InstRW<[P5600WriteMoveFPUToGPR], (instrs BC1F, BC1FL, BC1T, BC1TL, CFC1,
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| D | MipsScheduleGeneric.td | 800 BC1T, BC1FL, BC1TL)>;
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| /external/llvm-project/llvm/test/DebugInfo/MIR/Mips/ |
| D | live-debug-values-reg-copy.mir | 193 BC1T killed $fcc0, %bb.2, implicit-def dead $at, debug-location !19
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_common.c | 143 #define BC1T (HI(17) | (8 << 21) | (1 << 16)) macro
1826 inst = BC1T | JUMP_LENGTH; \
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenAsmWriter.inc | 2021 24045U, // BC1T
4775 0U, // BC1T
7586 {Mips::BC1T, 18, 1 },
7801 // Mips::BC1T - 18
8218 // (BC1T FCC0, brtarget:$offset) - 34
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| D | MipsGenSubtargetInfo.inc | 944 {DBGFIELD("BC1T") 1, false, false, 14, 2, 2, 1, 0, 0}, // #684
2628 {DBGFIELD("BC1T") 2, false, false, 68, 4, 2, 1, 0, 0}, // #684
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| D | MipsGenMCCodeEmitter.inc | 793 UINT64_C(1157693440), // BC1T
3194 case Mips::BC1T:
10255 CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1T = 780
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 202 23461U, // BC1T
1991 0U, // BC1T
5361 // (BC1T FCC0, brtarget:$offset)
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 1552 case Mips::BC1T: in processInstruction()
|