| /external/XNNPACK/src/qs8-gemm/ |
| D | 4x16c4-aarch64-neondot-ld32.S | 43 BIC x2, x2, 3
111 BIC v4.16b, v16.16b, v2.16b
112 BIC v5.16b, v17.16b, v2.16b
113 BIC v6.16b, v18.16b, v2.16b
114 BIC v7.16b, v19.16b, v2.16b
126 BIC v4.16b, v20.16b, v2.16b
127 BIC v5.16b, v21.16b, v2.16b
128 BIC v6.16b, v22.16b, v2.16b
129 BIC v7.16b, v23.16b, v2.16b
141 BIC v4.16b, v24.16b, v2.16b
[all …]
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| D | 4x16c4-aarch64-neondot-ld64.S | 43 BIC x2, x2, 3
134 BIC v4.16b, v16.16b, v2.16b
135 BIC v5.16b, v17.16b, v2.16b
136 BIC v6.16b, v18.16b, v2.16b
137 BIC v7.16b, v19.16b, v2.16b
149 BIC v4.16b, v20.16b, v2.16b
150 BIC v5.16b, v21.16b, v2.16b
151 BIC v6.16b, v22.16b, v2.16b
152 BIC v7.16b, v23.16b, v2.16b
164 BIC v4.16b, v24.16b, v2.16b
[all …]
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| D | 1x16c4-aarch64-neondot-ld32.S | 33 BIC x2, x2, 3
60 BIC v28.16b, v28.16b, v2.16b
61 BIC v29.16b, v29.16b, v2.16b
62 BIC v30.16b, v30.16b, v2.16b
63 BIC v31.16b, v31.16b, v2.16b
|
| D | 1x16c4-aarch64-neondot-ld64.S | 30 BIC x2, x2, 3
78 BIC v28.16b, v28.16b, v2.16b
79 BIC v29.16b, v29.16b, v2.16b
80 BIC v30.16b, v30.16b, v2.16b
81 BIC v31.16b, v31.16b, v2.16b
|
| D | 4x16c4-aarch64-neondot-cortex-a55.S | 51 BIC x2, x2, 3
419 BIC v16.16b, v16.16b, v2.16b
420 BIC v17.16b, v17.16b, v2.16b
421 BIC v18.16b, v18.16b, v2.16b
422 BIC v19.16b, v19.16b, v2.16b
423 BIC v20.16b, v20.16b, v2.16b
424 BIC v21.16b, v21.16b, v2.16b
425 BIC v22.16b, v22.16b, v2.16b
426 BIC v23.16b, v23.16b, v2.16b
446 BIC v24.16b, v24.16b, v2.16b
[all …]
|
| D | 2x8c8-aarch64-neon-mull-padal.S | 44 BIC x2, x2, 7
132 BIC v6.16b, v0.16b, v4.16b
133 BIC v16.16b, v1.16b, v4.16b
134 BIC v17.16b, v2.16b, v4.16b
135 BIC v4.16b, v3.16b, v4.16b
|
| D | 2x8c16-aarch64-neon-mlal-padal.S | 44 BIC x2, x2, 15
149 BIC v6.16b, v0.16b, v4.16b
150 BIC v16.16b, v1.16b, v4.16b
151 BIC v17.16b, v2.16b, v4.16b
152 BIC v4.16b, v3.16b, v4.16b
|
| D | 2x8c8-aarch64-neon-mlal-padal.S | 44 BIC x2, x2, 7
239 BIC v6.16b, v0.16b, v4.16b
240 BIC v16.16b, v1.16b, v4.16b
241 BIC v17.16b, v2.16b, v4.16b
242 BIC v4.16b, v3.16b, v4.16b
|
| /external/XNNPACK/src/qs8-igemm/ |
| D | 4x16c4-aarch64-neondot-ld64.S | 49 BIC x2, x2, 3
157 BIC v4.16b, v16.16b, v2.16b
158 BIC v5.16b, v17.16b, v2.16b
159 BIC v6.16b, v18.16b, v2.16b
160 BIC v7.16b, v19.16b, v2.16b
172 BIC v4.16b, v20.16b, v2.16b
173 BIC v5.16b, v21.16b, v2.16b
174 BIC v6.16b, v22.16b, v2.16b
175 BIC v7.16b, v23.16b, v2.16b
187 BIC v4.16b, v24.16b, v2.16b
[all …]
|
| D | 4x16c4-aarch64-neondot-cortex-a55.S | 54 BIC x2, x2, 3
444 BIC v16.16b, v16.16b, v2.16b
445 BIC v17.16b, v17.16b, v2.16b
446 BIC v18.16b, v18.16b, v2.16b
447 BIC v19.16b, v19.16b, v2.16b
448 BIC v20.16b, v20.16b, v2.16b
449 BIC v21.16b, v21.16b, v2.16b
450 BIC v22.16b, v22.16b, v2.16b
451 BIC v23.16b, v23.16b, v2.16b
471 BIC v24.16b, v24.16b, v2.16b
[all …]
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| D | 2x8c16-aarch64-neon-mlal-padal.S | 46 BIC x2, x2, 15
168 BIC v6.16b, v0.16b, v4.16b
169 BIC v16.16b, v1.16b, v4.16b
170 BIC v17.16b, v2.16b, v4.16b
171 BIC v4.16b, v3.16b, v4.16b
|
| D | 2x8c8-aarch64-neon-mlal-padal.S | 45 BIC x2, x2, 7
181 BIC v6.16b, v0.16b, v4.16b
182 BIC v16.16b, v1.16b, v4.16b
183 BIC v17.16b, v2.16b, v4.16b
184 BIC v4.16b, v3.16b, v4.16b
|
| /external/arm-neon-tests/ |
| D | InitCache.s | 20 ;BIC r0, r0, #(0x1 <<12) ; Clear bit 0
22 ;BIC r0, r0, #(0x1 << 2) ; Clear bit 0
32 ;BIC r0, r0, #(0x1 << 1) ; L2EN bit, disable L2 cache
44 ;BIC r0, r0, #(0x1 << 11) ; Disable all forms of branch prediction
|
| /external/llvm-project/llvm/test/MC/ARM/ |
| D | negative-immediates.s | 22 BIC r0, r1, #0xFFFFFF00
25 # CHECK-DISABLED: BIC
113 BIC r0, r1, #0xFFFFFF00
116 # CHECK-DISABLED: BIC
117 BIC.W r0, r1, #0xFFFFFF00
120 # CHECK-DISABLED: BIC.W
129 BIC r0, r1, #0xFEFFFEFF
132 # CHECK-DISABLED: BIC
|
| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_conv_ergtoamplitude.s | 50 BIC R11, R11, #1
77 BIC R11, R11, #1
105 BIC R11, R11, #1
|
| D | ixheaacd_conv_ergtoamplitudelp.s | 51 BIC R6, R6, #1
77 BIC R6, R6, #1
105 BIC R6, R6, #1
|
| D | ixheaacd_rescale_subbandsamples.s | 134 BIC R7, R3, #1
183 BIC R7, R3, #1
|
| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | arm-abi-attr.ll | 13 ; The stack is 8 byte aligned on AAPCS and 4 on APCS, so we should get a BIC
|
| /external/llvm/test/CodeGen/ARM/ |
| D | arm-abi-attr.ll | 13 ; The stack is 8 byte aligned on AAPCS and 4 on APCS, so we should get a BIC
|
| /external/vixl/test/aarch32/config/ |
| D | cond-rd-rn-operand-rm-t32.json | 69 "Bic", // BIC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
70 // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
232 "Bic", // BIC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | optimize-imm.ll | 52 ; a BIC.
|
| /external/tremolo/Tremolo/ |
| D | bitwiseARM.s | 204 BIC r3,r3,#3 @ r3 = Pointer to start (word)
229 BIC r2,r3,#3 @ r2 = b->headptr (word)
332 BIC r2,r6,#3 @ r2 = word ptr
369 BIC r2,r6,#3 @ r2 = word ptr
|
| D | dpen.s | 150 BIC r10,r10,#0x80 @ r3 = next &= ~0x80
169 BIC r7, r7, #0x8000 @ r7 = chase
210 BIC r10,r10,#0x8000 @ r3 = next &= ~0x8000
227 BIC r7, r7, #0x80000000 @ r7 = chase
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SchedTSV110.td | 361 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "(BIC|EON|ORN)[WX]rr")>;
362 def : InstRW<[TSV110Wr_1cyc_1AB], (instregex "(BIC)S[WX]rr")>;
367 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(ADC|SBC|BIC)[WX]r$")>;
370 def : InstRW<[TSV110Wr_2cyc_1MDU], (instregex "^(AND|BIC|EON|EOR|ORN|ORR)[WX]rs$")>;
371 def : InstRW<[TSV110Wr_2cyc_1AB], (instregex "^(AND|BIC|EON|EOR|ORN|ORR)S[WX]rs$")>;
550 def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(AND|BIC|BIF|BIT|BSL|EOR|MVN|NOT|ORN|ORR)v")…
|
| /external/OpenCSD/decoder/tests/snapshots/TC2/ds5-dumps/ |
| D | etmv3_0x12.txt | 80 Instruction 75 S:0xC0021288 0xF42253FF 1 BIC r3,r2,#0x1fe0 false
82 Instruction 77 S:0xC002128E 0xF023031F 0 BIC r3,r3,#0x1f false
91 Instruction 86 S:0xC0021494 0xF42253FF 1 BIC r3,r2,#0x1fe0 false
92 Instruction 87 S:0xC0021498 0xF023031F 1 BIC r3,r3,#0x1f false
94 Instruction 89 S:0xC002149E 0xF0234378 2 BIC r3,r3,#0xf8000000 false
95 Instruction 90 S:0xC00214A2 0xF02303FF 1 BIC r3,r3,#0xff false
119 Instruction 112 S:0xC0021288 0xF42253FF 1 BIC r3,r2,#0x1fe0 false
121 Instruction 114 S:0xC002128E 0xF023031F 0 BIC r3,r3,#0x1f false
130 Instruction 123 S:0xC0021494 0xF42253FF 1 BIC r3,r2,#0x1fe0 false
131 Instruction 124 S:0xC0021498 0xF023031F 1 BIC r3,r3,#0x1f false
[all …]
|