| /external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| D | legalize-bitreverse.mir | 13 ; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY1]]
15 ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE]], [[C]](s32)
34 ; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY1]]
36 ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE]], [[C]](s32)
55 ; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY1]]
57 ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE]], [[C]](s32)
75 ; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY]]
76 ; CHECK: $vgpr0 = COPY [[BITREVERSE]](s32)
94 ; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY1]]
95 ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE]], [[C]](s32)
[all …]
|
| D | regbankselect-bitreverse.mir | 14 ; CHECK: [[BITREVERSE:%[0-9]+]]:sgpr(s32) = G_BITREVERSE [[COPY]]
28 ; CHECK: [[BITREVERSE:%[0-9]+]]:vgpr(s32) = G_BITREVERSE [[COPY]]
|
| /external/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 949 { ISD::BITREVERSE, MVT::v4i64, 4 }, in getIntrinsicInstrCost()
950 { ISD::BITREVERSE, MVT::v8i32, 4 }, in getIntrinsicInstrCost()
951 { ISD::BITREVERSE, MVT::v16i16, 4 }, in getIntrinsicInstrCost()
952 { ISD::BITREVERSE, MVT::v32i8, 4 }, in getIntrinsicInstrCost()
953 { ISD::BITREVERSE, MVT::v2i64, 1 }, in getIntrinsicInstrCost()
954 { ISD::BITREVERSE, MVT::v4i32, 1 }, in getIntrinsicInstrCost()
955 { ISD::BITREVERSE, MVT::v8i16, 1 }, in getIntrinsicInstrCost()
956 { ISD::BITREVERSE, MVT::v16i8, 1 }, in getIntrinsicInstrCost()
957 { ISD::BITREVERSE, MVT::i64, 3 }, in getIntrinsicInstrCost()
958 { ISD::BITREVERSE, MVT::i32, 3 }, in getIntrinsicInstrCost()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 1910 { ISD::BITREVERSE, MVT::v8i64, 5 }, in getIntrinsicInstrCost()
1911 { ISD::BITREVERSE, MVT::v16i32, 5 }, in getIntrinsicInstrCost()
1912 { ISD::BITREVERSE, MVT::v32i16, 5 }, in getIntrinsicInstrCost()
1913 { ISD::BITREVERSE, MVT::v64i8, 5 }, in getIntrinsicInstrCost()
1936 { ISD::BITREVERSE, MVT::v8i64, 36 }, in getIntrinsicInstrCost()
1937 { ISD::BITREVERSE, MVT::v16i32, 24 }, in getIntrinsicInstrCost()
1954 { ISD::BITREVERSE, MVT::v4i64, 4 }, in getIntrinsicInstrCost()
1955 { ISD::BITREVERSE, MVT::v8i32, 4 }, in getIntrinsicInstrCost()
1956 { ISD::BITREVERSE, MVT::v16i16, 4 }, in getIntrinsicInstrCost()
1957 { ISD::BITREVERSE, MVT::v32i8, 4 }, in getIntrinsicInstrCost()
[all …]
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 2311 { ISD::BITREVERSE, MVT::v8i64, 5 }, in getTypeBasedIntrinsicInstrCost()
2312 { ISD::BITREVERSE, MVT::v16i32, 5 }, in getTypeBasedIntrinsicInstrCost()
2313 { ISD::BITREVERSE, MVT::v32i16, 5 }, in getTypeBasedIntrinsicInstrCost()
2314 { ISD::BITREVERSE, MVT::v64i8, 5 }, in getTypeBasedIntrinsicInstrCost()
2351 { ISD::BITREVERSE, MVT::v8i64, 36 }, in getTypeBasedIntrinsicInstrCost()
2352 { ISD::BITREVERSE, MVT::v16i32, 24 }, in getTypeBasedIntrinsicInstrCost()
2353 { ISD::BITREVERSE, MVT::v32i16, 10 }, in getTypeBasedIntrinsicInstrCost()
2354 { ISD::BITREVERSE, MVT::v64i8, 10 }, in getTypeBasedIntrinsicInstrCost()
2417 { ISD::BITREVERSE, MVT::v4i64, 4 }, in getTypeBasedIntrinsicInstrCost()
2418 { ISD::BITREVERSE, MVT::v8i32, 4 }, in getTypeBasedIntrinsicInstrCost()
[all …]
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 285 case ISD::BITREVERSE: in LegalizeOp()
699 case ISD::BITREVERSE: in Expand()
892 if (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, VT.getScalarType())) in ExpandBITREVERSE()
905 (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, ByteVT) || in ExpandBITREVERSE()
914 Op = DAG.getNode(ISD::BITREVERSE, DL, ByteVT, Op); in ExpandBITREVERSE()
|
| D | SelectionDAGDumper.cpp | 316 case ISD::BITREVERSE: return "bitreverse"; in getOperationName()
|
| D | LegalizeIntegerTypes.cpp | 56 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break; in PromoteIntegerResult()
333 ISD::SRL, dl, NVT, DAG.getNode(ISD::BITREVERSE, dl, NVT, Op), in PromoteIntRes_BITREVERSE()
1314 case ISD::BITREVERSE: ExpandIntRes_BITREVERSE(N, Lo, Hi); break; in ExpandIntegerResult()
1933 Lo = DAG.getNode(ISD::BITREVERSE, dl, Lo.getValueType(), Lo); in ExpandIntRes_BITREVERSE()
1934 Hi = DAG.getNode(ISD::BITREVERSE, dl, Hi.getValueType(), Hi); in ExpandIntRes_BITREVERSE()
|
| D | LegalizeVectorTypes.cpp | 70 case ISD::BITREVERSE: in ScalarizeVectorResult()
627 case ISD::BITREVERSE: in SplitVectorResult()
2148 case ISD::BITREVERSE: in WidenVectorResult()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 342 BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE, enumerator
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 474 BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE, enumerator
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 619 BITREVERSE, enumerator
|
| D | BasicTTIImpl.h | 1726 ISDs.push_back(ISD::BITREVERSE); in getTypeBasedIntrinsicInstrCost()
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 390 case ISD::BITREVERSE: in LegalizeOp()
771 case ISD::BITREVERSE: in Expand()
1103 if (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, VT.getScalarType())) { in ExpandBITREVERSE()
1119 (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, ByteVT) || in ExpandBITREVERSE()
1128 Op = DAG.getNode(ISD::BITREVERSE, DL, ByteVT, Op); in ExpandBITREVERSE()
|
| D | SelectionDAGDumper.cpp | 413 case ISD::BITREVERSE: return "bitreverse"; in getOperationName()
|
| D | LegalizeIntegerTypes.cpp | 59 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break; in PromoteIntegerResult()
469 DAG.getNode(ISD::BITREVERSE, dl, NVT, Op), in PromoteIntRes_BITREVERSE()
2033 case ISD::BITREVERSE: ExpandIntRes_BITREVERSE(N, Lo, Hi); break; in ExpandIntegerResult()
2849 Lo = DAG.getNode(ISD::BITREVERSE, dl, Lo.getValueType(), Lo); in ExpandIntRes_BITREVERSE()
2850 Hi = DAG.getNode(ISD::BITREVERSE, dl, Hi.getValueType(), Hi); in ExpandIntRes_BITREVERSE()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 394 case ISD::BITREVERSE: in LegalizeOp()
890 case ISD::BITREVERSE: in Expand()
1204 if (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, VT.getScalarType())) { in ExpandBITREVERSE()
1220 (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, ByteVT) || in ExpandBITREVERSE()
1229 Op = DAG.getNode(ISD::BITREVERSE, DL, ByteVT, Op); in ExpandBITREVERSE()
|
| D | SelectionDAGDumper.cpp | 393 case ISD::BITREVERSE: return "bitreverse"; in getOperationName()
|
| D | LegalizeIntegerTypes.cpp | 59 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break; in PromoteIntegerResult()
420 DAG.getNode(ISD::BITREVERSE, dl, NVT, Op), in PromoteIntRes_BITREVERSE()
1805 case ISD::BITREVERSE: ExpandIntRes_BITREVERSE(N, Lo, Hi); break; in ExpandIntegerResult()
2572 Lo = DAG.getNode(ISD::BITREVERSE, dl, Lo.getValueType(), Lo); in ExpandIntRes_BITREVERSE()
2573 Hi = DAG.getNode(ISD::BITREVERSE, dl, Hi.getValueType(), Hi); in ExpandIntRes_BITREVERSE()
|
| /external/llvm-project/llvm/test/Transforms/InstCombine/ |
| D | or-concat.ll | 123 ; BITREVERSE
|
| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 214 setOperationAction(ISD::BITREVERSE, XLenVT, Custom); in RISCVTargetLowering()
218 setOperationAction(ISD::BITREVERSE, MVT::i32, Custom); in RISCVTargetLowering()
583 case ISD::BITREVERSE: { in LowerOperation()
1199 case ISD::BITREVERSE: { in ReplaceNodeResults()
1204 unsigned Imm = N->getOpcode() == ISD::BITREVERSE ? 31 : 24; in ReplaceNodeResults()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 687 setOperationAction(ISD::BITREVERSE, VT, Expand); in initActions()
|
| /external/llvm-project/llvm/lib/Target/VE/ |
| D | VEISelLowering.cpp | 185 setOperationAction(ISD::BITREVERSE, IntVT, Act); in initSPUActions()
|
| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 890 setOperationAction(ISD::BITREVERSE, VT, Expand); in initActions()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1417 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); in HexagonTargetLowering()
1418 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); in HexagonTargetLowering()
|