| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | machine-outliner-bti.mir | 3 # AArch64 Branch Target Enforcement treats the BR and BLR indirect branch
4 # instructions differently. The BLR instruction can only target a BTI C
7 # transform a BLR instruction into a BR instruction.
35 BLR renamable $x19, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
38 BLR renamable $x19, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
41 …BLR killed renamable $x19, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
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| D | machine-outliner-2fixup-blr-terminator.mir | 27 BLR $x20, implicit $sp
46 BLR $x20, implicit $sp
65 BLR $x20, implicit $sp
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| D | speculation-hardening-sls-blr.mir | 6 # Check that the BLR SLS hardening transforms a BLR into a BL with operands as
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| D | chkstk.ll | 33 ; CHECK-REGSTATE-LARGE: frame-setup BLR killed $x16, implicit-def $lr, implicit $sp, implicit-def $…
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| D | speculation-hardening.mir | 145 BLR killed renamable $x17, implicit-def dead $lr, implicit $sp
174 … BLR killed renamable $lr, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $w0
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| /external/llvm-project/llvm/test/CodeGen/PowerPC/ |
| D | early-ret.mir | 24 BLR implicit $lr, implicit $rm, implicit killed $r3
30 ; CHECK: BLR implicit $lr, implicit $rm, implicit killed $r3
33 ; CHECK: BLR implicit $lr, implicit $rm, implicit killed $r3
63 BLR implicit $lr, implicit $rm, implicit killed $v2
74 ; CHECK: BLR implicit $lr, implicit $rm, implicit killed $v2
104 BLR implicit $lr, implicit $rm, implicit killed $v2
115 ; CHECK: BLR implicit $lr, implicit $rm, implicit killed $v2
136 BLR implicit $lr, implicit $rm
145 ; CHECK: BLR implicit $lr, implicit $rm
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| D | aix-print-pc.mir | 22 BLR implicit $lr, implicit $rm, implicit killed $r3
26 BLR implicit $lr, implicit $rm, implicit killed $r3
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| D | early-ret-verify.mir | 39 BLR implicit $lr, implicit $rm
59 ; CHECK: BLR implicit $lr, implicit $rm
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| D | quadint-return.ll | 19 ; CHECK-NEXT: BLR
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| D | aix32-crsave.mir | 18 BLR implicit $lr, implicit $rm, implicit $r3
55 BLR implicit $lr, implicit $rm, implicit $r3
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| D | ifcvt.mir | 48 BLR implicit $lr, implicit $rm
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| D | sh-overflow.mir | 28 BLR implicit $lr, implicit $rm, implicit killed $r3
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| D | stack-coloring-vararg.mir | 160 BLR implicit $lr, implicit $rm
169 BLR implicit $lr, implicit $rm
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| D | kernel-fp-round.ll | 28 ; CHECK-P6-NEXT: BLR implicit $lr, implicit $rm, implicit $f1
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| D | aix-xcoff-reloc-symb.mir | 19 BLR implicit $lr, implicit $rm, implicit killed $r3
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| D | aix32-cc-abi-vaarg.ll | 81 ; 32BIT-DAG: BLR implicit $lr, implicit $rm, implicit $r3
168 ; 32BIT-DAG: BLR implicit $lr, implicit $rm, implicit $r3
242 ; 32BIT-DAG: BLR implicit $lr, implicit $rm, implicit $f1
350 ; 32BIT-DAG: BLR implicit $lr, implicit $rm, implicit $f1
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| D | aix-cc-byval-mem.ll | 60 ; 32BIT-NEXT: BLR
160 ; 32BIT-NEXT: BLR
263 ; 32BIT-NEXT: BLR implicit $lr, implicit $rm
417 ; 32BIT-NEXT: BLR implicit $lr, implicit $rm
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SLSHardening.cpp | 111 case AArch64::BLR: in isBLR()
277 MachineInstr &BLR = *MBBI; in ConvertBLRToBL() local
278 assert(isBLR(BLR)); in ConvertBLRToBL()
282 switch (BLR.getOpcode()) { in ConvertBLRToBL()
283 case AArch64::BLR: in ConvertBLRToBL()
286 Reg = BLR.getOperand(0).getReg(); in ConvertBLRToBL()
288 RegIsKilled = BLR.getOperand(0).isKill(); in ConvertBLRToBL()
299 DebugLoc DL = BLR.getDebugLoc(); in ConvertBLRToBL()
362 BL->copyImplicitOps(MF, BLR); in ConvertBLRToBL()
363 MF.moveCallSiteInfo(&BLR, BL); in ConvertBLRToBL()
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| D | AArch64SchedPredExynos.td | 27 // Identify BLR specifying the LR register as the indirect target register.
29 CheckAll<[CheckOpcode<[BLR]>,
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| /external/llvm-project/compiler-rt/lib/xray/ |
| D | xray_trampoline_AArch64.S | 45 BLR X2
98 BLR X2
149 BLR X2
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedPredExynos.td | 27 // Identify BLR specifying the LR register as the indirect target register.
29 CheckAll<[CheckOpcode<[BLR]>,
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | quadint-return.ll | 19 ; CHECK-NEXT: BLR
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCEarlyReturn.cpp | 60 (I->getOpcode() != PPC::BLR && I->getOpcode() != PPC::BLR8) || in processBlock()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCEarlyReturn.cpp | 65 (I->getOpcode() != PPC::BLR && I->getOpcode() != PPC::BLR8) || in processBlock()
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCEarlyReturn.cpp | 60 (I->getOpcode() != PPC::BLR && I->getOpcode() != PPC::BLR8) || in processBlock()
|