| /external/OpenCSD/decoder/tests/snapshots/tc2-ptm-rstk-t32/ds-5_trace_dump/ |
| D | a15_rs.txt | 78 S:0x80000574 FA00008C BLX {pc}+0x238 ; 0x800007ac
108 S:0x800008FE 4788 BLX r1
122 S:0x8000091E 4788 BLX r1
140 S:0x8000091E 4788 BLX r1
172 S:0x80000998 4788 BLX r1
280 S:0x800007F2 4790 BLX r2
292 S:0x800007F2 4790 BLX r2
304 S:0x800007F2 4790 BLX r2
316 S:0x800007F2 4790 BLX r2
328 S:0x800007F2 4790 BLX r2
[all …]
|
| /external/llvm-project/compiler-rt/lib/xray/ |
| D | xray_trampoline_arm.S | 34 BLX r2
66 BLX r2
99 BLX r2
|
| /external/llvm-project/llvm/test/MC/ARM/ |
| D | thumb-not-mclass.s | 12 @ BLX (immediate)
|
| D | basic-thumb-instructions.s | 151 @ BL/BLX
178 @ BL/BLX (immediate)
194 @ BLX (register)
|
| /external/llvm/test/MC/ARM/ |
| D | thumb-not-mclass.s | 12 @ BLX (immediate)
|
| D | basic-thumb-instructions.s | 151 @ BL/BLX
178 @ BL/BLX (immediate)
194 @ BLX (register)
|
| /external/llvm-project/llvm/test/CodeGen/ARM/GlobalISel/ |
| D | arm-call-lowering.ll | 29 ; V5T: BLX [[COPY]](p0), csr_aapcs, implicit-def $lr, implicit $sp
|
| D | irtranslator-varargs-lowering.ll | 76 ; ARM: BLX [[FPTRVREG]](p0), csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2,…
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_32.c | 91 #define BLX 0xe12fff30 macro
275 return push_inst(compiler, BLX | RM(TMP_REG1)); in emit_blx()
515 inst[1] = BLX | RM(TMP_REG1); in inline_set_jump_addr()
2263 …PTR_FAIL_IF(push_inst(compiler, (((type <= SLJIT_JUMP ? BX : BLX) | RM(TMP_REG1)) & ~COND_MASK) | … in sljit_emit_jump()
2517 return push_inst(compiler, (type <= SLJIT_JUMP ? BX : BLX) | RM(src)); in sljit_emit_ijump()
2522 return push_inst(compiler, (type <= SLJIT_JUMP ? BX : BLX) | RM(TMP_REG1)); in sljit_emit_ijump()
2539 FAIL_IF(push_inst(compiler, (type <= SLJIT_JUMP ? BX : BLX) | RM(TMP_REG1))); in sljit_emit_ijump()
|
| D | sljitNativeARM_T2_32.c | 116 #define BLX 0x4780 macro
1860 PTR_FAIL_IF(push_inst16(compiler, BLX | RN3(TMP_REG1))); in sljit_emit_jump()
2114 return push_inst16(compiler, (type <= SLJIT_JUMP ? BX : BLX) | RN3(src)); in sljit_emit_ijump()
2119 return push_inst16(compiler, BLX | RN3(TMP_REG1)); in sljit_emit_ijump()
2130 return push_inst16(compiler, (type <= SLJIT_JUMP ? BX : BLX) | RN3(TMP_REG1)); in sljit_emit_ijump()
|
| /external/llvm-project/compiler-rt/lib/sanitizer_common/ |
| D | sanitizer_linux.cpp | 1633 # define BLX(R) "blx " #R "\n" in internal_clone() macro
1635 # define BLX(R) "mov lr, pc; bx " #R "\n" in internal_clone() macro
1638 # define BLX(R) "mov lr, pc; mov pc," #R "\n" in internal_clone() macro
1662 BLX(ip) in internal_clone()
|
| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 108 # BLX (register)
|
| D | basic-arm-instructions.txt | 354 # BLX (register)
363 # BLX (immediate)
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 108 # BLX (register)
|
| D | basic-arm-instructions.txt | 354 # BLX (register)
363 # BLX (immediate)
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMCallLowering.cpp | 491 return ARM::BLX; in getCallOpcode()
|
| D | ARMScheduleA57.td | 157 // B, BX, BL, BLX (imm, reg != LR, reg == LR), CBZ, CBNZ
163 def : InstRW<[A57Write_2cyc_1B_1I], (instregex "BLX", "tBLX(NS)?r")>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMCallLowering.cpp | 494 return ARM::BLX; in getCallOpcode()
|
| D | ARMScheduleA57.td | 169 // B, BX, BL, BLX (imm, reg != LR, reg == LR), CBZ, CBNZ
175 def : InstRW<[A57Write_2cyc_1B_1I], (instregex "BLX", "tBLX(NS)?r")>;
|
| D | ARMExpandPseudoInsts.cpp | 1429 TII->get(Thumb ? ARM::tBLXr : ARM::BLX)); in ExpandMI()
|
| /external/capstone/ |
| D | ChangeLog | 344 - BLX instruction modifies PC & LR registers.
426 - BL & BLX do not read SP, but PC register.
|
| /external/OpenCSD/decoder/tests/snapshots/TC2/ds5-dumps/ |
| D | ptmv1_0x13.txt | 90 Instruction 75 S:0xC00368EA 0x4798 142 BLX r3 true
149 Instruction 130 S:0xC0054218 0x4798 481 BLX r3 true
199 Instruction 176 S:0xC004F572 0x4788 398 BLX r1 true
322 Instruction 297 S:0xC004F572 0x4788 321 BLX r1 true
409 Instruction 382 S:0xC00542F2 0x4790 19 BLX r2 true
478 Instruction 447 S:0xC00368EA 0x4798 253 BLX r3 true
498 Instruction 465 S:0xC00368EA 0x4798 211 BLX r3 true
913 Instruction 858 S:0xC00368EA 0x4798 195 BLX r3 true
936 Instruction 881 S:0xC00139E4 0x4798 1 BLX r3 true
1069 Instruction 1008 S:0xC00368EA 0x4798 28 BLX r3 true
[all …]
|
| D | etmv3_0x12.txt | 190 Instruction 177 S:0xC000ED34 0x4798 1 BLX r3 true
195 Instruction 182 S:0xC00113F8 0x4798 1 BLX r3 true
351 Instruction 335 S:0xC003CC50 0x4798 1 BLX r3 true
1449 Instruction 1416 S:0xC004F572 0x4788 1 BLX r1 true
1537 Instruction 1501 S:0xC00542F2 0x4790 1 BLX r2 true
1671 Instruction 1628 S:0xC0020EFC 0x4798 1 BLX r3 true
1881 Instruction 1834 S:0xC0020EFC 0x4798 1 BLX r3 true
|
| D | etmv3_0x10.txt | 43 Instruction 37 S:0xC004EFB2 0x4798 1 BLX r3 true
210 Instruction 191 S:0xC004EFB2 0x4798 1 BLX r3 true
882 Instruction 824 S:0xC004EFB2 0x4798 1 BLX r3 true
1442 Instruction 1323 S:0xC000ED34 0x4798 1 BLX r3 true
1447 Instruction 1328 S:0xC00113F8 0x4798 1 BLX r3 true
1505 Instruction 1383 S:0xC003B858 0x4798 1 BLX r3 true
2806 Instruction 2656 S:0xC00368EA 0x4798 1 BLX r3 true
3160 Instruction 2986 S:0xC0050EE2 0x4798 1 BLX r3 true
3311 Instruction 3132 S:0xC0035108 0x47C8 1 BLX r9 true
3346 Instruction 3167 S:0xC004F572 0x4788 1 BLX r1 true
[all …]
|
| D | etmv3_0x11.txt | 342 Instruction 326 S:0xC00389DA 0x47E0 1 BLX r12 true
398 Instruction 380 S:0xC003D4E4 0x4790 1 BLX r2 true
421 Instruction 403 S:0xC003D4F0 0x4798 1 BLX r3 true
818 Instruction 791 S:0xC000ED34 0x4798 1 BLX r3 true
823 Instruction 796 S:0xC00113F8 0x4798 1 BLX r3 true
864 Instruction 834 S:0xC003B8AE 0x4798 1 BLX r3 true
1804 Instruction 1763 S:0xC003BEDC 0x4798 1 BLX r3 true
2260 Instruction 2211 S:0xC003CC50 0x4798 1 BLX r3 true
3288 Instruction 3219 S:0xC004F572 0x4788 1 BLX r1 true
3376 Instruction 3304 S:0xC00542F2 0x4790 1 BLX r2 true
[all …]
|