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Searched refs:BRW_ADDRESS_DIRECT (Results 1 – 13 of 13) sorted by relevance

/external/igt-gpu-tools/assembler/
Dgen8_disasm.c390 assert(gen8_dst_address_mode(inst) == BRW_ADDRESS_DIRECT); in dest()
404 assert(gen8_dst_address_mode(inst) == BRW_ADDRESS_DIRECT); in dest()
731 assert(gen8_src0_address_mode(inst) == BRW_ADDRESS_DIRECT); in src0()
745 assert(gen8_src0_address_mode(inst) == BRW_ADDRESS_DIRECT); in src0()
769 assert(gen8_src1_address_mode(inst) == BRW_ADDRESS_DIRECT); in src1()
783 assert(gen8_src1_address_mode(inst) == BRW_ADDRESS_DIRECT); in src1()
Dgen8_instruction.c50 if (reg.address_mode == BRW_ADDRESS_DIRECT) { in gen8_set_dst()
185 } else if (reg.address_mode == BRW_ADDRESS_DIRECT) { in gen8_set_src0()
274 } else if (reg.address_mode == BRW_ADDRESS_DIRECT) { in gen8_set_src1()
Dgram.y73 .address_mode = BRW_ADDRESS_DIRECT,
82 .reg.address_mode = BRW_ADDRESS_DIRECT,
288 if (reg->address_mode == BRW_ADDRESS_DIRECT && in validate_dst_reg()
387 assert(address_mode == BRW_ADDRESS_DIRECT); in get_subreg_address()
424 if (reg->address_mode == BRW_ADDRESS_DIRECT) in resolve_subnr()
1177 src0.reg.address_mode = BRW_ADDRESS_DIRECT;
1300 src0.reg.address_mode = BRW_ADDRESS_DIRECT;
1350 src0.reg.address_mode = BRW_ADDRESS_DIRECT;
2112 $$.address_mode = BRW_ADDRESS_DIRECT;
2117 $$.address_mode = BRW_ADDRESS_DIRECT;
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Dbrw_disasm.c519 if (inst->bits1.da1.dest_address_mode == BRW_ADDRESS_DIRECT) in dest()
545 if (inst->bits1.da16.dest_address_mode == BRW_ADDRESS_DIRECT) in dest()
892 if (inst->bits2.da1.src0_address_mode == BRW_ADDRESS_DIRECT) in src0()
922 if (inst->bits2.da16.src0_address_mode == BRW_ADDRESS_DIRECT) in src0()
952 if (inst->bits3.da1.src1_address_mode == BRW_ADDRESS_DIRECT) in src1()
982 if (inst->bits3.da16.src1_address_mode == BRW_ADDRESS_DIRECT) in src1()
Dbrw_eu_emit.c118 if (dest.address_mode == BRW_ADDRESS_DIRECT) { in brw_set_dest()
266 assert(reg.address_mode == BRW_ADDRESS_DIRECT); in brw_set_src0()
293 if (reg.address_mode == BRW_ADDRESS_DIRECT) { in brw_set_src0()
382 assert (intel->gen >= 4 || reg.address_mode == BRW_ADDRESS_DIRECT); in brw_set_src1()
384 if (reg.address_mode == BRW_ADDRESS_DIRECT) { in brw_set_src1()
843 assert(dest.address_mode == BRW_ADDRESS_DIRECT); in brw_set_3src_dest()
858 assert(src0.address_mode == BRW_ADDRESS_DIRECT); in brw_set_3src_src0()
875 assert(src1.address_mode == BRW_ADDRESS_DIRECT); in brw_set_3src_src1()
893 assert(src2.address_mode == BRW_ADDRESS_DIRECT); in brw_set_3src_src2()
Dbrw_reg.h207 reg.address_mode = BRW_ADDRESS_DIRECT; in brw_reg()
Dbrw_defines.h551 #define BRW_ADDRESS_DIRECT 0 macro
/external/mesa3d/src/intel/compiler/
Dbrw_eu_validate.c174 return brw_inst_src0_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT && in src0_is_null()
442 ERROR_IF(brw_inst_src0_address_mode(devinfo, inst) != BRW_ADDRESS_DIRECT, in send_restrictions()
894 brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) { in general_restrictions_based_on_operand_types()
1111 ERROR_IF(brw_inst_src0_address_mode(devinfo, inst) != BRW_ADDRESS_DIRECT || in special_restrictions_for_mixed_float_mode()
1113 brw_inst_src1_address_mode(devinfo, inst) != BRW_ADDRESS_DIRECT), in special_restrictions_for_mixed_float_mode()
1233 if (brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) in special_restrictions_for_mixed_float_mode()
1395 BRW_ADDRESS_DIRECT) \ in region_alignment_rules()
Dbrw_disasm.c763 } else if (brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) { in dest()
781 if (brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) { in dest()
808 if (brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) { in dest()
1475 } else if (brw_inst_send_src0_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) { in src0()
1492 if (brw_inst_src0_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) { in src0()
1519 if (brw_inst_src0_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) { in src0()
1554 if (brw_inst_src1_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) { in src1()
1581 if (brw_inst_src1_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) { in src1()
Dbrw_eu_emit.c117 assert(dest.address_mode == BRW_ADDRESS_DIRECT); in brw_set_dest()
131 assert(dest.address_mode == BRW_ADDRESS_DIRECT); in brw_set_dest()
143 if (dest.address_mode == BRW_ADDRESS_DIRECT) { in brw_set_dest()
231 assert(reg.address_mode == BRW_ADDRESS_DIRECT); in brw_set_src0()
238 assert(reg.address_mode == BRW_ADDRESS_DIRECT); in brw_set_src0()
250 assert(reg.address_mode == BRW_ADDRESS_DIRECT); in brw_set_src0()
281 if (reg.address_mode == BRW_ADDRESS_DIRECT) { in brw_set_src0()
359 assert(reg.address_mode == BRW_ADDRESS_DIRECT); in brw_set_src1()
395 assert (reg.address_mode == BRW_ADDRESS_DIRECT); in brw_set_src1()
803 assert(dest.address_mode == BRW_ADDRESS_DIRECT); in brw_alu3()
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Dbrw_eu_defines.h100 #define BRW_ADDRESS_DIRECT 0 macro
Dbrw_reg.h429 reg.address_mode = BRW_ADDRESS_DIRECT; in brw_reg()
/external/mesa3d/src/intel/tools/
Di965_gram.y1565 $$.address_mode = BRW_ADDRESS_DIRECT;
1575 $$.address_mode = BRW_ADDRESS_DIRECT;