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Searched refs:BRW_ARF_ADDRESS (Results 1 – 14 of 14) sorted by relevance

/external/igt-gpu-tools/assembler/
Dbrw_reg.h522 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_ADDRESS, subnr); in brw_address_reg()
Dbrw_defines.h794 #define BRW_ARF_ADDRESS 0x10 macro
Dgen8_disasm.c344 case BRW_ARF_ADDRESS: in reg()
Dgram.y1335 ($7.reg.nr & 0xF0) != BRW_ARF_ADDRESS ||
2437 $$.nr = BRW_ARF_ADDRESS | $1;
3022 ((src->reg.nr & 0xF0) == BRW_ARF_ADDRESS)) { in reset_instruction_src_region()
Dbrw_disasm.c474 case BRW_ARF_ADDRESS: in reg()
/external/mesa3d/src/intel/compiler/
Dbrw_eu_defines.h994 #define BRW_ARF_ADDRESS 0x10 macro
Dbrw_reg.h841 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_ADDRESS, subnr); in brw_address_reg()
Dbrw_fs_scoreboard.cpp589 r.file == ARF && reg >= BRW_ARF_ADDRESS && in dep()
Dbrw_vec4.cpp1635 case BRW_ARF_ADDRESS: in dump_instruction()
1729 case BRW_ARF_ADDRESS: in dump_instruction()
Dbrw_ir_performance.cpp1197 } else if (r.file == ARF && r.nr >= BRW_ARF_ADDRESS && in reg_dependency_id()
Dbrw_eu_emit.c2784 assert(desc.nr == BRW_ARF_ADDRESS); in brw_send_indirect_split_message()
2794 assert(ex_desc.nr == BRW_ARF_ADDRESS); in brw_send_indirect_split_message()
Dbrw_disasm.c700 case BRW_ARF_ADDRESS: in reg()
Dbrw_fs.cpp7275 case BRW_ARF_ADDRESS: in dump_instruction()
7373 case BRW_ARF_ADDRESS: in dump_instruction()
/external/mesa3d/src/intel/tools/
Di965_gram.y1831 $$.nr = BRW_ARF_ADDRESS;