1 /*
2 * Copyright © 2010 - 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef BRW_COMPILER_H
25 #define BRW_COMPILER_H
26
27 #include <stdio.h>
28 #include "dev/gen_device_info.h"
29 #include "main/macros.h"
30 #include "main/mtypes.h"
31 #include "util/ralloc.h"
32
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36
37 struct ra_regs;
38 struct nir_shader;
39 struct brw_program;
40
41 typedef struct nir_shader nir_shader;
42
43 struct brw_compiler {
44 const struct gen_device_info *devinfo;
45
46 struct {
47 struct ra_regs *regs;
48
49 /**
50 * Array of the ra classes for the unaligned contiguous register
51 * block sizes used.
52 */
53 int *classes;
54
55 /**
56 * Mapping for register-allocated objects in *regs to the first
57 * GRF for that object.
58 */
59 uint8_t *ra_reg_to_grf;
60 } vec4_reg_set;
61
62 struct {
63 struct ra_regs *regs;
64
65 /**
66 * Array of the ra classes for the unaligned contiguous register
67 * block sizes used, indexed by register size.
68 */
69 int classes[16];
70
71 /**
72 * Mapping from classes to ra_reg ranges. Each of the per-size
73 * classes corresponds to a range of ra_reg nodes. This array stores
74 * those ranges in the form of first ra_reg in each class and the
75 * total number of ra_reg elements in the last array element. This
76 * way the range of the i'th class is given by:
77 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
78 */
79 int class_to_ra_reg_range[17];
80
81 /**
82 * Mapping for register-allocated objects in *regs to the first
83 * GRF for that object.
84 */
85 uint8_t *ra_reg_to_grf;
86
87 /**
88 * ra class for the aligned barycentrics we use for PLN, which doesn't
89 * appear in *classes.
90 */
91 int aligned_bary_class;
92 } fs_reg_sets[3];
93
94 void (*shader_debug_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
95 void (*shader_perf_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
96
97 bool scalar_stage[MESA_ALL_SHADER_STAGES];
98 bool use_tcs_8_patch;
99 struct gl_shader_compiler_options glsl_compiler_options[MESA_ALL_SHADER_STAGES];
100
101 /**
102 * Apply workarounds for SIN and COS output range problems.
103 * This can negatively impact performance.
104 */
105 bool precise_trig;
106
107 /**
108 * Is 3DSTATE_CONSTANT_*'s Constant Buffer 0 relative to Dynamic State
109 * Base Address? (If not, it's a normal GPU address.)
110 */
111 bool constant_buffer_0_is_relative;
112
113 /**
114 * Whether or not the driver supports pull constants. If not, the compiler
115 * will attempt to push everything.
116 */
117 bool supports_pull_constants;
118
119 /**
120 * Whether or not the driver supports NIR shader constants. This controls
121 * whether nir_opt_large_constants will be run.
122 */
123 bool supports_shader_constants;
124
125 /**
126 * Whether or not the driver wants uniform params to be compacted by the
127 * back-end compiler.
128 */
129 bool compact_params;
130
131 /**
132 * Whether or not the driver wants variable group size to be lowered by the
133 * back-end compiler.
134 */
135 bool lower_variable_group_size;
136
137 /**
138 * Whether indirect UBO loads should use the sampler or go through the
139 * data/constant cache. For the sampler, UBO surface states have to be set
140 * up with VK_FORMAT_R32G32B32A32_FLOAT whereas if it's going through the
141 * constant or data cache, UBOs must use VK_FORMAT_RAW.
142 */
143 bool indirect_ubos_use_sampler;
144 };
145
146 /**
147 * We use a constant subgroup size of 32. It really only needs to be a
148 * maximum and, since we do SIMD32 for compute shaders in some cases, it
149 * needs to be at least 32. SIMD8 and SIMD16 shaders will still claim a
150 * subgroup size of 32 but will act as if 16 or 24 of those channels are
151 * disabled.
152 */
153 #define BRW_SUBGROUP_SIZE 32
154
155 /**
156 * Program key structures.
157 *
158 * When drawing, we look for the currently bound shaders in the program
159 * cache. This is essentially a hash table lookup, and these are the keys.
160 *
161 * Sometimes OpenGL features specified as state need to be simulated via
162 * shader code, due to a mismatch between the API and the hardware. This
163 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
164 * in the program key so it's considered when searching for a program. If
165 * we haven't seen a particular combination before, we have to recompile a
166 * new specialized version.
167 *
168 * Shader compilation should not look up state in gl_context directly, but
169 * instead use the copy in the program key. This guarantees recompiles will
170 * happen correctly.
171 *
172 * @{
173 */
174
175 enum PACKED gen6_gather_sampler_wa {
176 WA_SIGN = 1, /* whether we need to sign extend */
177 WA_8BIT = 2, /* if we have an 8bit format needing wa */
178 WA_16BIT = 4, /* if we have a 16bit format needing wa */
179 };
180
181 /**
182 * Sampler information needed by VS, WM, and GS program cache keys.
183 */
184 struct brw_sampler_prog_key_data {
185 /**
186 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
187 */
188 uint16_t swizzles[MAX_SAMPLERS];
189
190 uint32_t gl_clamp_mask[3];
191
192 /**
193 * For RG32F, gather4's channel select is broken.
194 */
195 uint32_t gather_channel_quirk_mask;
196
197 /**
198 * Whether this sampler uses the compressed multisample surface layout.
199 */
200 uint32_t compressed_multisample_layout_mask;
201
202 /**
203 * Whether this sampler is using 16x multisampling. If so fetching from
204 * this sampler will be handled with a different instruction, ld2dms_w
205 * instead of ld2dms.
206 */
207 uint32_t msaa_16;
208
209 /**
210 * For Sandybridge, which shader w/a we need for gather quirks.
211 */
212 enum gen6_gather_sampler_wa gen6_gather_wa[MAX_SAMPLERS];
213
214 /**
215 * Texture units that have a YUV image bound.
216 */
217 uint32_t y_u_v_image_mask;
218 uint32_t y_uv_image_mask;
219 uint32_t yx_xuxv_image_mask;
220 uint32_t xy_uxvx_image_mask;
221 uint32_t ayuv_image_mask;
222 uint32_t xyuv_image_mask;
223 uint32_t bt709_mask;
224 uint32_t bt2020_mask;
225
226 /* Scale factor for each texture. */
227 float scale_factors[32];
228 };
229
230 /** An enum representing what kind of input gl_SubgroupSize is. */
231 enum PACKED brw_subgroup_size_type
232 {
233 BRW_SUBGROUP_SIZE_API_CONSTANT, /**< Default Vulkan behavior */
234 BRW_SUBGROUP_SIZE_UNIFORM, /**< OpenGL behavior */
235 BRW_SUBGROUP_SIZE_VARYING, /**< VK_EXT_subgroup_size_control */
236
237 /* These enums are specifically chosen so that the value of the enum is
238 * also the subgroup size. If any new values are added, they must respect
239 * this invariant.
240 */
241 BRW_SUBGROUP_SIZE_REQUIRE_8 = 8, /**< VK_EXT_subgroup_size_control */
242 BRW_SUBGROUP_SIZE_REQUIRE_16 = 16, /**< VK_EXT_subgroup_size_control */
243 BRW_SUBGROUP_SIZE_REQUIRE_32 = 32, /**< VK_EXT_subgroup_size_control */
244 };
245
246 struct brw_base_prog_key {
247 unsigned program_string_id;
248
249 enum brw_subgroup_size_type subgroup_size_type;
250
251 struct brw_sampler_prog_key_data tex;
252 };
253
254 /**
255 * The VF can't natively handle certain types of attributes, such as GL_FIXED
256 * or most 10_10_10_2 types. These flags enable various VS workarounds to
257 * "fix" attributes at the beginning of shaders.
258 */
259 #define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */
260 #define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */
261 #define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */
262 #define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */
263 #define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */
264
265 /**
266 * OpenGL attribute slots fall in [0, VERT_ATTRIB_MAX - 1] with the range
267 * [VERT_ATTRIB_GENERIC0, VERT_ATTRIB_MAX - 1] reserved for up to 16 user
268 * input vertex attributes. In Vulkan, we expose up to 28 user vertex input
269 * attributes that are mapped to slots also starting at VERT_ATTRIB_GENERIC0.
270 */
271 #define MAX_GL_VERT_ATTRIB VERT_ATTRIB_MAX
272 #define MAX_VK_VERT_ATTRIB (VERT_ATTRIB_GENERIC0 + 28)
273
274 /** The program key for Vertex Shaders. */
275 struct brw_vs_prog_key {
276 struct brw_base_prog_key base;
277
278 /**
279 * Per-attribute workaround flags
280 *
281 * For each attribute, a combination of BRW_ATTRIB_WA_*.
282 *
283 * For OpenGL, where we expose a maximum of 16 user input atttributes
284 * we only need up to VERT_ATTRIB_MAX slots, however, in Vulkan
285 * slots preceding VERT_ATTRIB_GENERIC0 are unused and we can
286 * expose up to 28 user input vertex attributes that are mapped to slots
287 * starting at VERT_ATTRIB_GENERIC0, so this array needs to be large
288 * enough to hold this many slots.
289 */
290 uint8_t gl_attrib_wa_flags[MAX2(MAX_GL_VERT_ATTRIB, MAX_VK_VERT_ATTRIB)];
291
292 bool copy_edgeflag:1;
293
294 bool clamp_vertex_color:1;
295
296 /**
297 * How many user clipping planes are being uploaded to the vertex shader as
298 * push constants.
299 *
300 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
301 * clip distances.
302 */
303 unsigned nr_userclip_plane_consts:4;
304
305 /**
306 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
307 * are going to be replaced with point coordinates (as a consequence of a
308 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
309 * our SF thread requires exact matching between VS outputs and FS inputs,
310 * these texture coordinates will need to be unconditionally included in
311 * the VUE, even if they aren't written by the vertex shader.
312 */
313 uint8_t point_coord_replace;
314 };
315
316 /** The program key for Tessellation Control Shaders. */
317 struct brw_tcs_prog_key
318 {
319 struct brw_base_prog_key base;
320
321 GLenum tes_primitive_mode;
322
323 unsigned input_vertices;
324
325 /** A bitfield of per-patch outputs written. */
326 uint32_t patch_outputs_written;
327
328 /** A bitfield of per-vertex outputs written. */
329 uint64_t outputs_written;
330
331 bool quads_workaround;
332 };
333
334 /** The program key for Tessellation Evaluation Shaders. */
335 struct brw_tes_prog_key
336 {
337 struct brw_base_prog_key base;
338
339 /** A bitfield of per-patch inputs read. */
340 uint32_t patch_inputs_read;
341
342 /** A bitfield of per-vertex inputs read. */
343 uint64_t inputs_read;
344
345 /**
346 * How many user clipping planes are being uploaded to the tessellation
347 * evaluation shader as push constants.
348 *
349 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
350 * clip distances.
351 */
352 unsigned nr_userclip_plane_consts:4;
353 };
354
355 /** The program key for Geometry Shaders. */
356 struct brw_gs_prog_key
357 {
358 struct brw_base_prog_key base;
359
360 /**
361 * How many user clipping planes are being uploaded to the geometry shader
362 * as push constants.
363 *
364 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
365 * clip distances.
366 */
367 unsigned nr_userclip_plane_consts:4;
368 };
369
370 enum brw_sf_primitive {
371 BRW_SF_PRIM_POINTS = 0,
372 BRW_SF_PRIM_LINES = 1,
373 BRW_SF_PRIM_TRIANGLES = 2,
374 BRW_SF_PRIM_UNFILLED_TRIS = 3,
375 };
376
377 struct brw_sf_prog_key {
378 uint64_t attrs;
379 bool contains_flat_varying;
380 unsigned char interp_mode[65]; /* BRW_VARYING_SLOT_COUNT */
381 uint8_t point_sprite_coord_replace;
382 enum brw_sf_primitive primitive:2;
383 bool do_twoside_color:1;
384 bool frontface_ccw:1;
385 bool do_point_sprite:1;
386 bool do_point_coord:1;
387 bool sprite_origin_lower_left:1;
388 bool userclip_active:1;
389 };
390
391 enum brw_clip_mode {
392 BRW_CLIP_MODE_NORMAL = 0,
393 BRW_CLIP_MODE_CLIP_ALL = 1,
394 BRW_CLIP_MODE_CLIP_NON_REJECTED = 2,
395 BRW_CLIP_MODE_REJECT_ALL = 3,
396 BRW_CLIP_MODE_ACCEPT_ALL = 4,
397 BRW_CLIP_MODE_KERNEL_CLIP = 5,
398 };
399
400 enum brw_clip_fill_mode {
401 BRW_CLIP_FILL_MODE_LINE = 0,
402 BRW_CLIP_FILL_MODE_POINT = 1,
403 BRW_CLIP_FILL_MODE_FILL = 2,
404 BRW_CLIP_FILL_MODE_CULL = 3,
405 };
406
407 /* Note that if unfilled primitives are being emitted, we have to fix
408 * up polygon offset and flatshading at this point:
409 */
410 struct brw_clip_prog_key {
411 uint64_t attrs;
412 bool contains_flat_varying;
413 bool contains_noperspective_varying;
414 unsigned char interp_mode[65]; /* BRW_VARYING_SLOT_COUNT */
415 unsigned primitive:4;
416 unsigned nr_userclip:4;
417 bool pv_first:1;
418 bool do_unfilled:1;
419 enum brw_clip_fill_mode fill_cw:2; /* includes cull information */
420 enum brw_clip_fill_mode fill_ccw:2; /* includes cull information */
421 bool offset_cw:1;
422 bool offset_ccw:1;
423 bool copy_bfc_cw:1;
424 bool copy_bfc_ccw:1;
425 enum brw_clip_mode clip_mode:3;
426
427 float offset_factor;
428 float offset_units;
429 float offset_clamp;
430 };
431
432 /* A big lookup table is used to figure out which and how many
433 * additional regs will inserted before the main payload in the WM
434 * program execution. These mainly relate to depth and stencil
435 * processing and the early-depth-test optimization.
436 */
437 enum brw_wm_iz_bits {
438 BRW_WM_IZ_PS_KILL_ALPHATEST_BIT = 0x1,
439 BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT = 0x2,
440 BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT = 0x4,
441 BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT = 0x8,
442 BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT = 0x10,
443 BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT = 0x20,
444 BRW_WM_IZ_BIT_MAX = 0x40
445 };
446
447 enum brw_wm_aa_enable {
448 BRW_WM_AA_NEVER,
449 BRW_WM_AA_SOMETIMES,
450 BRW_WM_AA_ALWAYS
451 };
452
453 /** The program key for Fragment/Pixel Shaders. */
454 struct brw_wm_prog_key {
455 struct brw_base_prog_key base;
456
457 /* Some collection of BRW_WM_IZ_* */
458 uint8_t iz_lookup;
459 bool stats_wm:1;
460 bool flat_shade:1;
461 unsigned nr_color_regions:5;
462 bool alpha_test_replicate_alpha:1;
463 bool alpha_to_coverage:1;
464 bool clamp_fragment_color:1;
465 bool persample_interp:1;
466 bool multisample_fbo:1;
467 bool frag_coord_adds_sample_pos:1;
468 enum brw_wm_aa_enable line_aa:2;
469 bool high_quality_derivatives:1;
470 bool force_dual_color_blend:1;
471 bool coherent_fb_fetch:1;
472 bool ignore_sample_mask_out:1;
473
474 uint8_t color_outputs_valid;
475 uint64_t input_slots_valid;
476 GLenum alpha_test_func; /* < For Gen4/5 MRT alpha test */
477 float alpha_test_ref;
478 };
479
480 struct brw_cs_prog_key {
481 struct brw_base_prog_key base;
482 };
483
484 /* brw_any_prog_key is any of the keys that map to an API stage */
485 union brw_any_prog_key {
486 struct brw_base_prog_key base;
487 struct brw_vs_prog_key vs;
488 struct brw_tcs_prog_key tcs;
489 struct brw_tes_prog_key tes;
490 struct brw_gs_prog_key gs;
491 struct brw_wm_prog_key wm;
492 struct brw_cs_prog_key cs;
493 };
494
495 /*
496 * Image metadata structure as laid out in the shader parameter
497 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
498 * able to use them. That's okay because the padding and any unused
499 * entries [most of them except when we're doing untyped surface
500 * access] will be removed by the uniform packing pass.
501 */
502 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 0
503 #define BRW_IMAGE_PARAM_SIZE_OFFSET 4
504 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 8
505 #define BRW_IMAGE_PARAM_TILING_OFFSET 12
506 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 16
507 #define BRW_IMAGE_PARAM_SIZE 20
508
509 struct brw_image_param {
510 /** Offset applied to the X and Y surface coordinates. */
511 uint32_t offset[2];
512
513 /** Surface X, Y and Z dimensions. */
514 uint32_t size[3];
515
516 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
517 * pixels, vertical slice stride in pixels.
518 */
519 uint32_t stride[4];
520
521 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
522 uint32_t tiling[3];
523
524 /**
525 * Right shift to apply for bit 6 address swizzling. Two different
526 * swizzles can be specified and will be applied one after the other. The
527 * resulting address will be:
528 *
529 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
530 * (addr >> swizzling[1])))
531 *
532 * Use \c 0xff if any of the swizzles is not required.
533 */
534 uint32_t swizzling[2];
535 };
536
537 /** Max number of render targets in a shader */
538 #define BRW_MAX_DRAW_BUFFERS 8
539
540 /**
541 * Max number of binding table entries used for stream output.
542 *
543 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
544 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
545 *
546 * On Gen6, the size of transform feedback data is limited not by the number
547 * of components but by the number of binding table entries we set aside. We
548 * use one binding table entry for a float, one entry for a vector, and one
549 * entry per matrix column. Since the only way we can communicate our
550 * transform feedback capabilities to the client is via
551 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
552 * worst case, in which all the varyings are floats, so we use up one binding
553 * table entry per component. Therefore we need to set aside at least 64
554 * binding table entries for use by transform feedback.
555 *
556 * Note: since we don't currently pack varyings, it is currently impossible
557 * for the client to actually use up all of these binding table entries--if
558 * all of their varyings were floats, they would run out of varying slots and
559 * fail to link. But that's a bug, so it seems prudent to go ahead and
560 * allocate the number of binding table entries we will need once the bug is
561 * fixed.
562 */
563 #define BRW_MAX_SOL_BINDINGS 64
564
565 /**
566 * Binding table index for the first gen6 SOL binding.
567 */
568 #define BRW_GEN6_SOL_BINDING_START 0
569
570 /**
571 * Stride in bytes between shader_time entries.
572 *
573 * We separate entries by a cacheline to reduce traffic between EUs writing to
574 * different entries.
575 */
576 #define BRW_SHADER_TIME_STRIDE 64
577
578 struct brw_ubo_range
579 {
580 uint16_t block;
581 uint8_t start;
582 uint8_t length;
583 };
584
585 /* We reserve the first 2^16 values for builtins */
586 #define BRW_PARAM_IS_BUILTIN(param) (((param) & 0xffff0000) == 0)
587
588 enum brw_param_builtin {
589 BRW_PARAM_BUILTIN_ZERO,
590
591 BRW_PARAM_BUILTIN_CLIP_PLANE_0_X,
592 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Y,
593 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Z,
594 BRW_PARAM_BUILTIN_CLIP_PLANE_0_W,
595 BRW_PARAM_BUILTIN_CLIP_PLANE_1_X,
596 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Y,
597 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Z,
598 BRW_PARAM_BUILTIN_CLIP_PLANE_1_W,
599 BRW_PARAM_BUILTIN_CLIP_PLANE_2_X,
600 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Y,
601 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Z,
602 BRW_PARAM_BUILTIN_CLIP_PLANE_2_W,
603 BRW_PARAM_BUILTIN_CLIP_PLANE_3_X,
604 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Y,
605 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Z,
606 BRW_PARAM_BUILTIN_CLIP_PLANE_3_W,
607 BRW_PARAM_BUILTIN_CLIP_PLANE_4_X,
608 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Y,
609 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Z,
610 BRW_PARAM_BUILTIN_CLIP_PLANE_4_W,
611 BRW_PARAM_BUILTIN_CLIP_PLANE_5_X,
612 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Y,
613 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Z,
614 BRW_PARAM_BUILTIN_CLIP_PLANE_5_W,
615 BRW_PARAM_BUILTIN_CLIP_PLANE_6_X,
616 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Y,
617 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Z,
618 BRW_PARAM_BUILTIN_CLIP_PLANE_6_W,
619 BRW_PARAM_BUILTIN_CLIP_PLANE_7_X,
620 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Y,
621 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Z,
622 BRW_PARAM_BUILTIN_CLIP_PLANE_7_W,
623
624 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X,
625 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y,
626 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Z,
627 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W,
628 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X,
629 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y,
630
631 BRW_PARAM_BUILTIN_PATCH_VERTICES_IN,
632
633 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_X,
634 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Y,
635 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Z,
636 BRW_PARAM_BUILTIN_SUBGROUP_ID,
637 BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_X,
638 BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_Y,
639 BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_Z,
640 BRW_PARAM_BUILTIN_WORK_DIM,
641 };
642
643 #define BRW_PARAM_BUILTIN_CLIP_PLANE(idx, comp) \
644 (BRW_PARAM_BUILTIN_CLIP_PLANE_0_X + ((idx) << 2) + (comp))
645
646 #define BRW_PARAM_BUILTIN_IS_CLIP_PLANE(param) \
647 ((param) >= BRW_PARAM_BUILTIN_CLIP_PLANE_0_X && \
648 (param) <= BRW_PARAM_BUILTIN_CLIP_PLANE_7_W)
649
650 #define BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(param) \
651 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) >> 2)
652
653 #define BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(param) \
654 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) & 0x3)
655
656 /** Represents a code relocation
657 *
658 * Relocatable constants are immediates in the code which we want to be able
659 * to replace post-compile with the actual value.
660 */
661 struct brw_shader_reloc {
662 /** The 32-bit ID of the relocatable constant */
663 uint32_t id;
664
665 /** The offset in the shader to the relocatable instruction
666 *
667 * This is the offset to the instruction rather than the immediate value
668 * itself. This allows us to do some sanity checking while we relocate.
669 */
670 uint32_t offset;
671 };
672
673 /** A value to write to a relocation */
674 struct brw_shader_reloc_value {
675 /** The 32-bit ID of the relocatable constant */
676 uint32_t id;
677
678 /** The value with which to replace the relocated immediate */
679 uint32_t value;
680 };
681
682 struct brw_stage_prog_data {
683 struct {
684 /** size of our binding table. */
685 uint32_t size_bytes;
686
687 /** @{
688 * surface indices for the various groups of surfaces
689 */
690 uint32_t pull_constants_start;
691 uint32_t texture_start;
692 uint32_t gather_texture_start;
693 uint32_t ubo_start;
694 uint32_t ssbo_start;
695 uint32_t image_start;
696 uint32_t shader_time_start;
697 uint32_t plane_start[3];
698 /** @} */
699 } binding_table;
700
701 struct brw_ubo_range ubo_ranges[4];
702
703 GLuint nr_params; /**< number of float params/constants */
704 GLuint nr_pull_params;
705
706 /* zero_push_reg is a bitfield which indicates what push registers (if any)
707 * should be zeroed by SW at the start of the shader. The corresponding
708 * push_reg_mask_param specifies the param index (in 32-bit units) where
709 * the actual runtime 64-bit mask will be pushed. The shader will zero
710 * push reg i if
711 *
712 * reg_used & zero_push_reg & ~*push_reg_mask_param & (1ull << i)
713 *
714 * If this field is set, brw_compiler::compact_params must be false.
715 */
716 uint64_t zero_push_reg;
717 unsigned push_reg_mask_param;
718
719 unsigned curb_read_length;
720 unsigned total_scratch;
721 unsigned total_shared;
722
723 unsigned program_size;
724
725 unsigned const_data_size;
726 unsigned const_data_offset;
727
728 unsigned num_relocs;
729 const struct brw_shader_reloc *relocs;
730
731 /** Does this program pull from any UBO or other constant buffers? */
732 bool has_ubo_pull;
733
734 /**
735 * Register where the thread expects to find input data from the URB
736 * (typically uniforms, followed by vertex or fragment attributes).
737 */
738 unsigned dispatch_grf_start_reg;
739
740 bool use_alt_mode; /**< Use ALT floating point mode? Otherwise, IEEE. */
741
742 /* 32-bit identifiers for all push/pull parameters. These can be anything
743 * the driver wishes them to be; the core of the back-end compiler simply
744 * re-arranges them. The one restriction is that the bottom 2^16 values
745 * are reserved for builtins defined in the brw_param_builtin enum defined
746 * above.
747 */
748 uint32_t *param;
749 uint32_t *pull_param;
750
751 /* Whether shader uses atomic operations. */
752 bool uses_atomic_load_store;
753 };
754
755 static inline uint32_t *
brw_stage_prog_data_add_params(struct brw_stage_prog_data * prog_data,unsigned nr_new_params)756 brw_stage_prog_data_add_params(struct brw_stage_prog_data *prog_data,
757 unsigned nr_new_params)
758 {
759 unsigned old_nr_params = prog_data->nr_params;
760 prog_data->nr_params += nr_new_params;
761 prog_data->param = reralloc(ralloc_parent(prog_data->param),
762 prog_data->param, uint32_t,
763 prog_data->nr_params);
764 return prog_data->param + old_nr_params;
765 }
766
767 enum brw_barycentric_mode {
768 BRW_BARYCENTRIC_PERSPECTIVE_PIXEL = 0,
769 BRW_BARYCENTRIC_PERSPECTIVE_CENTROID = 1,
770 BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE = 2,
771 BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL = 3,
772 BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID = 4,
773 BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE = 5,
774 BRW_BARYCENTRIC_MODE_COUNT = 6
775 };
776 #define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
777 ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
778 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
779 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
780
781 enum brw_pixel_shader_computed_depth_mode {
782 BRW_PSCDEPTH_OFF = 0, /* PS does not compute depth */
783 BRW_PSCDEPTH_ON = 1, /* PS computes depth; no guarantee about value */
784 BRW_PSCDEPTH_ON_GE = 2, /* PS guarantees output depth >= source depth */
785 BRW_PSCDEPTH_ON_LE = 3, /* PS guarantees output depth <= source depth */
786 };
787
788 /* Data about a particular attempt to compile a program. Note that
789 * there can be many of these, each in a different GL state
790 * corresponding to a different brw_wm_prog_key struct, with different
791 * compiled programs.
792 */
793 struct brw_wm_prog_data {
794 struct brw_stage_prog_data base;
795
796 GLuint num_varying_inputs;
797
798 uint8_t reg_blocks_8;
799 uint8_t reg_blocks_16;
800 uint8_t reg_blocks_32;
801
802 uint8_t dispatch_grf_start_reg_16;
803 uint8_t dispatch_grf_start_reg_32;
804 uint32_t prog_offset_16;
805 uint32_t prog_offset_32;
806
807 struct {
808 /** @{
809 * surface indices the WM-specific surfaces
810 */
811 uint32_t render_target_read_start;
812 /** @} */
813 } binding_table;
814
815 uint8_t computed_depth_mode;
816 bool computed_stencil;
817
818 bool early_fragment_tests;
819 bool post_depth_coverage;
820 bool inner_coverage;
821 bool dispatch_8;
822 bool dispatch_16;
823 bool dispatch_32;
824 bool dual_src_blend;
825 bool persample_dispatch;
826 bool uses_pos_offset;
827 bool uses_omask;
828 bool uses_kill;
829 bool uses_src_depth;
830 bool uses_src_w;
831 bool uses_sample_mask;
832 bool has_render_target_reads;
833 bool has_side_effects;
834 bool pulls_bary;
835
836 bool contains_flat_varying;
837 bool contains_noperspective_varying;
838
839 /**
840 * Mask of which interpolation modes are required by the fragment shader.
841 * Used in hardware setup on gen6+.
842 */
843 uint32_t barycentric_interp_modes;
844
845 /**
846 * Mask of which FS inputs are marked flat by the shader source. This is
847 * needed for setting up 3DSTATE_SF/SBE.
848 */
849 uint32_t flat_inputs;
850
851 /**
852 * The FS inputs
853 */
854 uint64_t inputs;
855
856 /* Mapping of VUE slots to interpolation modes.
857 * Used by the Gen4-5 clip/sf/wm stages.
858 */
859 unsigned char interp_mode[65]; /* BRW_VARYING_SLOT_COUNT */
860
861 /**
862 * Map from gl_varying_slot to the position within the FS setup data
863 * payload where the varying's attribute vertex deltas should be delivered.
864 * For varying slots that are not used by the FS, the value is -1.
865 */
866 int urb_setup[VARYING_SLOT_MAX];
867
868 /**
869 * Cache structure into the urb_setup array above that contains the
870 * attribute numbers of active varyings out of urb_setup.
871 * The actual count is stored in urb_setup_attribs_count.
872 */
873 uint8_t urb_setup_attribs[VARYING_SLOT_MAX];
874 uint8_t urb_setup_attribs_count;
875 };
876
877 /** Returns the SIMD width corresponding to a given KSP index
878 *
879 * The "Variable Pixel Dispatch" table in the PRM (which can be found, for
880 * example in Vol. 7 of the SKL PRM) has a mapping from dispatch widths to
881 * kernel start pointer (KSP) indices that is based on what dispatch widths
882 * are enabled. This function provides, effectively, the reverse mapping.
883 *
884 * If the given KSP is valid with respect to the SIMD8/16/32 enables, a SIMD
885 * width of 8, 16, or 32 is returned. If the KSP is invalid, 0 is returned.
886 */
887 static inline unsigned
brw_fs_simd_width_for_ksp(unsigned ksp_idx,bool simd8_enabled,bool simd16_enabled,bool simd32_enabled)888 brw_fs_simd_width_for_ksp(unsigned ksp_idx, bool simd8_enabled,
889 bool simd16_enabled, bool simd32_enabled)
890 {
891 /* This function strictly ignores contiguous dispatch */
892 switch (ksp_idx) {
893 case 0:
894 return simd8_enabled ? 8 :
895 (simd16_enabled && !simd32_enabled) ? 16 :
896 (simd32_enabled && !simd16_enabled) ? 32 : 0;
897 case 1:
898 return (simd32_enabled && (simd16_enabled || simd8_enabled)) ? 32 : 0;
899 case 2:
900 return (simd16_enabled && (simd32_enabled || simd8_enabled)) ? 16 : 0;
901 default:
902 unreachable("Invalid KSP index");
903 }
904 }
905
906 #define brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx) \
907 brw_fs_simd_width_for_ksp((ksp_idx), (wm_state)._8PixelDispatchEnable, \
908 (wm_state)._16PixelDispatchEnable, \
909 (wm_state)._32PixelDispatchEnable)
910
911 #define brw_wm_state_has_ksp(wm_state, ksp_idx) \
912 (brw_wm_state_simd_width_for_ksp((wm_state), (ksp_idx)) != 0)
913
914 static inline uint32_t
_brw_wm_prog_data_prog_offset(const struct brw_wm_prog_data * prog_data,unsigned simd_width)915 _brw_wm_prog_data_prog_offset(const struct brw_wm_prog_data *prog_data,
916 unsigned simd_width)
917 {
918 switch (simd_width) {
919 case 8: return 0;
920 case 16: return prog_data->prog_offset_16;
921 case 32: return prog_data->prog_offset_32;
922 default: return 0;
923 }
924 }
925
926 #define brw_wm_prog_data_prog_offset(prog_data, wm_state, ksp_idx) \
927 _brw_wm_prog_data_prog_offset(prog_data, \
928 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
929
930 static inline uint8_t
_brw_wm_prog_data_dispatch_grf_start_reg(const struct brw_wm_prog_data * prog_data,unsigned simd_width)931 _brw_wm_prog_data_dispatch_grf_start_reg(const struct brw_wm_prog_data *prog_data,
932 unsigned simd_width)
933 {
934 switch (simd_width) {
935 case 8: return prog_data->base.dispatch_grf_start_reg;
936 case 16: return prog_data->dispatch_grf_start_reg_16;
937 case 32: return prog_data->dispatch_grf_start_reg_32;
938 default: return 0;
939 }
940 }
941
942 #define brw_wm_prog_data_dispatch_grf_start_reg(prog_data, wm_state, ksp_idx) \
943 _brw_wm_prog_data_dispatch_grf_start_reg(prog_data, \
944 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
945
946 static inline uint8_t
_brw_wm_prog_data_reg_blocks(const struct brw_wm_prog_data * prog_data,unsigned simd_width)947 _brw_wm_prog_data_reg_blocks(const struct brw_wm_prog_data *prog_data,
948 unsigned simd_width)
949 {
950 switch (simd_width) {
951 case 8: return prog_data->reg_blocks_8;
952 case 16: return prog_data->reg_blocks_16;
953 case 32: return prog_data->reg_blocks_32;
954 default: return 0;
955 }
956 }
957
958 #define brw_wm_prog_data_reg_blocks(prog_data, wm_state, ksp_idx) \
959 _brw_wm_prog_data_reg_blocks(prog_data, \
960 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
961
962 struct brw_push_const_block {
963 unsigned dwords; /* Dword count, not reg aligned */
964 unsigned regs;
965 unsigned size; /* Bytes, register aligned */
966 };
967
968 struct brw_cs_prog_data {
969 struct brw_stage_prog_data base;
970
971 unsigned local_size[3];
972
973 /* Program offsets for the 8/16/32 SIMD variants. Multiple variants are
974 * kept when using variable group size, and the right one can only be
975 * decided at dispatch time.
976 */
977 unsigned prog_offset[3];
978
979 /* Bitmask indicating which program offsets are valid. */
980 unsigned prog_mask;
981
982 /* Bitmask indicating which programs have spilled. */
983 unsigned prog_spilled;
984
985 bool uses_barrier;
986 bool uses_num_work_groups;
987
988 struct {
989 struct brw_push_const_block cross_thread;
990 struct brw_push_const_block per_thread;
991 } push;
992
993 struct {
994 /** @{
995 * surface indices the CS-specific surfaces
996 */
997 uint32_t work_groups_start;
998 /** @} */
999 } binding_table;
1000 };
1001
1002 static inline uint32_t
brw_cs_prog_data_prog_offset(const struct brw_cs_prog_data * prog_data,unsigned dispatch_width)1003 brw_cs_prog_data_prog_offset(const struct brw_cs_prog_data *prog_data,
1004 unsigned dispatch_width)
1005 {
1006 assert(dispatch_width == 8 ||
1007 dispatch_width == 16 ||
1008 dispatch_width == 32);
1009 const unsigned index = dispatch_width / 16;
1010 assert(prog_data->prog_mask & (1 << index));
1011 return prog_data->prog_offset[index];
1012 }
1013
1014 /**
1015 * Enum representing the i965-specific vertex results that don't correspond
1016 * exactly to any element of gl_varying_slot. The values of this enum are
1017 * assigned such that they don't conflict with gl_varying_slot.
1018 */
1019 typedef enum
1020 {
1021 BRW_VARYING_SLOT_NDC = VARYING_SLOT_MAX,
1022 BRW_VARYING_SLOT_PAD,
1023 /**
1024 * Technically this is not a varying but just a placeholder that
1025 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
1026 * builtin variable to be compiled correctly. see compile_sf_prog() for
1027 * more info.
1028 */
1029 BRW_VARYING_SLOT_PNTC,
1030 BRW_VARYING_SLOT_COUNT
1031 } brw_varying_slot;
1032
1033 /**
1034 * We always program SF to start reading at an offset of 1 (2 varying slots)
1035 * from the start of the vertex URB entry. This causes it to skip:
1036 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
1037 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
1038 */
1039 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
1040
1041 /**
1042 * Bitmask indicating which fragment shader inputs represent varyings (and
1043 * hence have to be delivered to the fragment shader by the SF/SBE stage).
1044 */
1045 #define BRW_FS_VARYING_INPUT_MASK \
1046 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
1047 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
1048
1049 /**
1050 * Data structure recording the relationship between the gl_varying_slot enum
1051 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
1052 * single octaword within the VUE (128 bits).
1053 *
1054 * Note that each BRW register contains 256 bits (2 octawords), so when
1055 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
1056 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
1057 * in a vertex shader), each register corresponds to a single VUE slot, since
1058 * it contains data for two separate vertices.
1059 */
1060 struct brw_vue_map {
1061 /**
1062 * Bitfield representing all varying slots that are (a) stored in this VUE
1063 * map, and (b) actually written by the shader. Does not include any of
1064 * the additional varying slots defined in brw_varying_slot.
1065 */
1066 uint64_t slots_valid;
1067
1068 /**
1069 * Is this VUE map for a separate shader pipeline?
1070 *
1071 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
1072 * without the linker having a chance to dead code eliminate unused varyings.
1073 *
1074 * This means that we have to use a fixed slot layout, based on the output's
1075 * location field, rather than assigning slots in a compact contiguous block.
1076 */
1077 bool separate;
1078
1079 /**
1080 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
1081 * not stored in a slot (because they are not written, or because
1082 * additional processing is applied before storing them in the VUE), the
1083 * value is -1.
1084 */
1085 signed char varying_to_slot[VARYING_SLOT_TESS_MAX];
1086
1087 /**
1088 * Map from VUE slot to gl_varying_slot value. For slots that do not
1089 * directly correspond to a gl_varying_slot, the value comes from
1090 * brw_varying_slot.
1091 *
1092 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
1093 */
1094 signed char slot_to_varying[VARYING_SLOT_TESS_MAX];
1095
1096 /**
1097 * Total number of VUE slots in use
1098 */
1099 int num_slots;
1100
1101 /**
1102 * Number of per-patch VUE slots. Only valid for tessellation control
1103 * shader outputs and tessellation evaluation shader inputs.
1104 */
1105 int num_per_patch_slots;
1106
1107 /**
1108 * Number of per-vertex VUE slots. Only valid for tessellation control
1109 * shader outputs and tessellation evaluation shader inputs.
1110 */
1111 int num_per_vertex_slots;
1112 };
1113
1114 void brw_print_vue_map(FILE *fp, const struct brw_vue_map *vue_map);
1115
1116 /**
1117 * Convert a VUE slot number into a byte offset within the VUE.
1118 */
brw_vue_slot_to_offset(GLuint slot)1119 static inline GLuint brw_vue_slot_to_offset(GLuint slot)
1120 {
1121 return 16*slot;
1122 }
1123
1124 /**
1125 * Convert a vertex output (brw_varying_slot) into a byte offset within the
1126 * VUE.
1127 */
1128 static inline
brw_varying_to_offset(const struct brw_vue_map * vue_map,GLuint varying)1129 GLuint brw_varying_to_offset(const struct brw_vue_map *vue_map, GLuint varying)
1130 {
1131 return brw_vue_slot_to_offset(vue_map->varying_to_slot[varying]);
1132 }
1133
1134 void brw_compute_vue_map(const struct gen_device_info *devinfo,
1135 struct brw_vue_map *vue_map,
1136 uint64_t slots_valid,
1137 bool separate_shader,
1138 uint32_t pos_slots);
1139
1140 void brw_compute_tess_vue_map(struct brw_vue_map *const vue_map,
1141 uint64_t slots_valid,
1142 uint32_t is_patch);
1143
1144 /* brw_interpolation_map.c */
1145 void brw_setup_vue_interpolation(struct brw_vue_map *vue_map,
1146 struct nir_shader *nir,
1147 struct brw_wm_prog_data *prog_data);
1148
1149 enum shader_dispatch_mode {
1150 DISPATCH_MODE_4X1_SINGLE = 0,
1151 DISPATCH_MODE_4X2_DUAL_INSTANCE = 1,
1152 DISPATCH_MODE_4X2_DUAL_OBJECT = 2,
1153 DISPATCH_MODE_SIMD8 = 3,
1154
1155 DISPATCH_MODE_TCS_SINGLE_PATCH = 0,
1156 DISPATCH_MODE_TCS_8_PATCH = 2,
1157 };
1158
1159 /**
1160 * @defgroup Tessellator parameter enumerations.
1161 *
1162 * These correspond to the hardware values in 3DSTATE_TE, and are provided
1163 * as part of the tessellation evaluation shader.
1164 *
1165 * @{
1166 */
1167 enum brw_tess_partitioning {
1168 BRW_TESS_PARTITIONING_INTEGER = 0,
1169 BRW_TESS_PARTITIONING_ODD_FRACTIONAL = 1,
1170 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL = 2,
1171 };
1172
1173 enum brw_tess_output_topology {
1174 BRW_TESS_OUTPUT_TOPOLOGY_POINT = 0,
1175 BRW_TESS_OUTPUT_TOPOLOGY_LINE = 1,
1176 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW = 2,
1177 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW = 3,
1178 };
1179
1180 enum brw_tess_domain {
1181 BRW_TESS_DOMAIN_QUAD = 0,
1182 BRW_TESS_DOMAIN_TRI = 1,
1183 BRW_TESS_DOMAIN_ISOLINE = 2,
1184 };
1185 /** @} */
1186
1187 struct brw_vue_prog_data {
1188 struct brw_stage_prog_data base;
1189 struct brw_vue_map vue_map;
1190
1191 /** Should the hardware deliver input VUE handles for URB pull loads? */
1192 bool include_vue_handles;
1193
1194 GLuint urb_read_length;
1195 GLuint total_grf;
1196
1197 uint32_t clip_distance_mask;
1198 uint32_t cull_distance_mask;
1199
1200 /* Used for calculating urb partitions. In the VS, this is the size of the
1201 * URB entry used for both input and output to the thread. In the GS, this
1202 * is the size of the URB entry used for output.
1203 */
1204 GLuint urb_entry_size;
1205
1206 enum shader_dispatch_mode dispatch_mode;
1207 };
1208
1209 struct brw_vs_prog_data {
1210 struct brw_vue_prog_data base;
1211
1212 GLbitfield64 inputs_read;
1213 GLbitfield64 double_inputs_read;
1214
1215 unsigned nr_attribute_slots;
1216
1217 bool uses_vertexid;
1218 bool uses_instanceid;
1219 bool uses_is_indexed_draw;
1220 bool uses_firstvertex;
1221 bool uses_baseinstance;
1222 bool uses_drawid;
1223 };
1224
1225 struct brw_tcs_prog_data
1226 {
1227 struct brw_vue_prog_data base;
1228
1229 /** Should the non-SINGLE_PATCH payload provide primitive ID? */
1230 bool include_primitive_id;
1231
1232 /** Number vertices in output patch */
1233 int instances;
1234
1235 /** Track patch count threshold */
1236 int patch_count_threshold;
1237 };
1238
1239
1240 struct brw_tes_prog_data
1241 {
1242 struct brw_vue_prog_data base;
1243
1244 enum brw_tess_partitioning partitioning;
1245 enum brw_tess_output_topology output_topology;
1246 enum brw_tess_domain domain;
1247 };
1248
1249 struct brw_gs_prog_data
1250 {
1251 struct brw_vue_prog_data base;
1252
1253 unsigned vertices_in;
1254
1255 /**
1256 * Size of an output vertex, measured in HWORDS (32 bytes).
1257 */
1258 unsigned output_vertex_size_hwords;
1259
1260 unsigned output_topology;
1261
1262 /**
1263 * Size of the control data (cut bits or StreamID bits), in hwords (32
1264 * bytes). 0 if there is no control data.
1265 */
1266 unsigned control_data_header_size_hwords;
1267
1268 /**
1269 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
1270 * if the control data is StreamID bits, or
1271 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
1272 * Ignored if control_data_header_size is 0.
1273 */
1274 unsigned control_data_format;
1275
1276 bool include_primitive_id;
1277
1278 /**
1279 * The number of vertices emitted, if constant - otherwise -1.
1280 */
1281 int static_vertex_count;
1282
1283 int invocations;
1284
1285 /**
1286 * Gen6: Provoking vertex convention for odd-numbered triangles
1287 * in tristrips.
1288 */
1289 GLuint pv_first:1;
1290
1291 /**
1292 * Gen6: Number of varyings that are output to transform feedback.
1293 */
1294 GLuint num_transform_feedback_bindings:7; /* 0-BRW_MAX_SOL_BINDINGS */
1295
1296 /**
1297 * Gen6: Map from the index of a transform feedback binding table entry to the
1298 * gl_varying_slot that should be streamed out through that binding table
1299 * entry.
1300 */
1301 unsigned char transform_feedback_bindings[64 /* BRW_MAX_SOL_BINDINGS */];
1302
1303 /**
1304 * Gen6: Map from the index of a transform feedback binding table entry to the
1305 * swizzles that should be used when streaming out data through that
1306 * binding table entry.
1307 */
1308 unsigned char transform_feedback_swizzles[64 /* BRW_MAX_SOL_BINDINGS */];
1309 };
1310
1311 struct brw_sf_prog_data {
1312 uint32_t urb_read_length;
1313 uint32_t total_grf;
1314
1315 /* Each vertex may have upto 12 attributes, 4 components each,
1316 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
1317 * rows.
1318 *
1319 * Actually we use 4 for each, so call it 12 rows.
1320 */
1321 unsigned urb_entry_size;
1322 };
1323
1324 struct brw_clip_prog_data {
1325 uint32_t curb_read_length; /* user planes? */
1326 uint32_t clip_mode;
1327 uint32_t urb_read_length;
1328 uint32_t total_grf;
1329 };
1330
1331 /* brw_any_prog_data is prog_data for any stage that maps to an API stage */
1332 union brw_any_prog_data {
1333 struct brw_stage_prog_data base;
1334 struct brw_vue_prog_data vue;
1335 struct brw_vs_prog_data vs;
1336 struct brw_tcs_prog_data tcs;
1337 struct brw_tes_prog_data tes;
1338 struct brw_gs_prog_data gs;
1339 struct brw_wm_prog_data wm;
1340 struct brw_cs_prog_data cs;
1341 };
1342
1343 #define DEFINE_PROG_DATA_DOWNCAST(stage) \
1344 static inline struct brw_##stage##_prog_data * \
1345 brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \
1346 { \
1347 return (struct brw_##stage##_prog_data *) prog_data; \
1348 } \
1349 static inline const struct brw_##stage##_prog_data * \
1350 brw_##stage##_prog_data_const(const struct brw_stage_prog_data *prog_data) \
1351 { \
1352 return (const struct brw_##stage##_prog_data *) prog_data; \
1353 }
1354 DEFINE_PROG_DATA_DOWNCAST(vue)
1355 DEFINE_PROG_DATA_DOWNCAST(vs)
1356 DEFINE_PROG_DATA_DOWNCAST(tcs)
1357 DEFINE_PROG_DATA_DOWNCAST(tes)
1358 DEFINE_PROG_DATA_DOWNCAST(gs)
1359 DEFINE_PROG_DATA_DOWNCAST(wm)
1360 DEFINE_PROG_DATA_DOWNCAST(cs)
1361 DEFINE_PROG_DATA_DOWNCAST(ff_gs)
1362 DEFINE_PROG_DATA_DOWNCAST(clip)
1363 DEFINE_PROG_DATA_DOWNCAST(sf)
1364 #undef DEFINE_PROG_DATA_DOWNCAST
1365
1366 struct brw_compile_stats {
1367 uint32_t dispatch_width; /**< 0 for vec4 */
1368 uint32_t instructions;
1369 uint32_t sends;
1370 uint32_t loops;
1371 uint32_t cycles;
1372 uint32_t spills;
1373 uint32_t fills;
1374 };
1375
1376 /** @} */
1377
1378 struct brw_compiler *
1379 brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo);
1380
1381 /**
1382 * Returns a compiler configuration for use with disk shader cache
1383 *
1384 * This value only needs to change for settings that can cause different
1385 * program generation between two runs on the same hardware.
1386 *
1387 * For example, it doesn't need to be different for gen 8 and gen 9 hardware,
1388 * but it does need to be different if INTEL_DEBUG=nocompact is or isn't used.
1389 */
1390 uint64_t
1391 brw_get_compiler_config_value(const struct brw_compiler *compiler);
1392
1393 unsigned
1394 brw_prog_data_size(gl_shader_stage stage);
1395
1396 unsigned
1397 brw_prog_key_size(gl_shader_stage stage);
1398
1399 void
1400 brw_prog_key_set_id(union brw_any_prog_key *key, gl_shader_stage, unsigned id);
1401
1402 /**
1403 * Compile a vertex shader.
1404 *
1405 * Returns the final assembly and the program's size.
1406 */
1407 const unsigned *
1408 brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
1409 void *mem_ctx,
1410 const struct brw_vs_prog_key *key,
1411 struct brw_vs_prog_data *prog_data,
1412 nir_shader *nir,
1413 int shader_time_index,
1414 struct brw_compile_stats *stats,
1415 char **error_str);
1416
1417 /**
1418 * Compile a tessellation control shader.
1419 *
1420 * Returns the final assembly and the program's size.
1421 */
1422 const unsigned *
1423 brw_compile_tcs(const struct brw_compiler *compiler,
1424 void *log_data,
1425 void *mem_ctx,
1426 const struct brw_tcs_prog_key *key,
1427 struct brw_tcs_prog_data *prog_data,
1428 nir_shader *nir,
1429 int shader_time_index,
1430 struct brw_compile_stats *stats,
1431 char **error_str);
1432
1433 /**
1434 * Compile a tessellation evaluation shader.
1435 *
1436 * Returns the final assembly and the program's size.
1437 */
1438 const unsigned *
1439 brw_compile_tes(const struct brw_compiler *compiler, void *log_data,
1440 void *mem_ctx,
1441 const struct brw_tes_prog_key *key,
1442 const struct brw_vue_map *input_vue_map,
1443 struct brw_tes_prog_data *prog_data,
1444 nir_shader *nir,
1445 int shader_time_index,
1446 struct brw_compile_stats *stats,
1447 char **error_str);
1448
1449 /**
1450 * Compile a vertex shader.
1451 *
1452 * Returns the final assembly and the program's size.
1453 */
1454 const unsigned *
1455 brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
1456 void *mem_ctx,
1457 const struct brw_gs_prog_key *key,
1458 struct brw_gs_prog_data *prog_data,
1459 nir_shader *nir,
1460 struct gl_program *prog,
1461 int shader_time_index,
1462 struct brw_compile_stats *stats,
1463 char **error_str);
1464
1465 /**
1466 * Compile a strips and fans shader.
1467 *
1468 * This is a fixed-function shader determined entirely by the shader key and
1469 * a VUE map.
1470 *
1471 * Returns the final assembly and the program's size.
1472 */
1473 const unsigned *
1474 brw_compile_sf(const struct brw_compiler *compiler,
1475 void *mem_ctx,
1476 const struct brw_sf_prog_key *key,
1477 struct brw_sf_prog_data *prog_data,
1478 struct brw_vue_map *vue_map,
1479 unsigned *final_assembly_size);
1480
1481 /**
1482 * Compile a clipper shader.
1483 *
1484 * This is a fixed-function shader determined entirely by the shader key and
1485 * a VUE map.
1486 *
1487 * Returns the final assembly and the program's size.
1488 */
1489 const unsigned *
1490 brw_compile_clip(const struct brw_compiler *compiler,
1491 void *mem_ctx,
1492 const struct brw_clip_prog_key *key,
1493 struct brw_clip_prog_data *prog_data,
1494 struct brw_vue_map *vue_map,
1495 unsigned *final_assembly_size);
1496
1497 /**
1498 * Compile a fragment shader.
1499 *
1500 * Returns the final assembly and the program's size.
1501 */
1502 const unsigned *
1503 brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
1504 void *mem_ctx,
1505 const struct brw_wm_prog_key *key,
1506 struct brw_wm_prog_data *prog_data,
1507 nir_shader *nir,
1508 int shader_time_index8,
1509 int shader_time_index16,
1510 int shader_time_index32,
1511 bool allow_spilling,
1512 bool use_rep_send, struct brw_vue_map *vue_map,
1513 struct brw_compile_stats *stats, /**< Array of three stats */
1514 char **error_str);
1515
1516 /**
1517 * Compile a compute shader.
1518 *
1519 * Returns the final assembly and the program's size.
1520 */
1521 const unsigned *
1522 brw_compile_cs(const struct brw_compiler *compiler, void *log_data,
1523 void *mem_ctx,
1524 const struct brw_cs_prog_key *key,
1525 struct brw_cs_prog_data *prog_data,
1526 const nir_shader *nir,
1527 int shader_time_index,
1528 struct brw_compile_stats *stats,
1529 char **error_str);
1530
1531 void brw_debug_key_recompile(const struct brw_compiler *c, void *log,
1532 gl_shader_stage stage,
1533 const struct brw_base_prog_key *old_key,
1534 const struct brw_base_prog_key *key);
1535
1536 static inline uint32_t
encode_slm_size(unsigned gen,uint32_t bytes)1537 encode_slm_size(unsigned gen, uint32_t bytes)
1538 {
1539 uint32_t slm_size = 0;
1540
1541 /* Shared Local Memory is specified as powers of two, and encoded in
1542 * INTERFACE_DESCRIPTOR_DATA with the following representations:
1543 *
1544 * Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB |
1545 * -------------------------------------------------------------------
1546 * Gen7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 |
1547 * -------------------------------------------------------------------
1548 * Gen9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1549 */
1550 assert(bytes <= 64 * 1024);
1551
1552 if (bytes > 0) {
1553 /* Shared Local Memory Size is specified as powers of two. */
1554 slm_size = util_next_power_of_two(bytes);
1555
1556 if (gen >= 9) {
1557 /* Use a minimum of 1kB; turn an exponent of 10 (1024 kB) into 1. */
1558 slm_size = ffs(MAX2(slm_size, 1024)) - 10;
1559 } else {
1560 /* Use a minimum of 4kB; convert to the pre-Gen9 representation. */
1561 slm_size = MAX2(slm_size, 4096) / 4096;
1562 }
1563 }
1564
1565 return slm_size;
1566 }
1567
1568 unsigned
1569 brw_cs_push_const_total_size(const struct brw_cs_prog_data *cs_prog_data,
1570 unsigned threads);
1571
1572 unsigned
1573 brw_cs_simd_size_for_group_size(const struct gen_device_info *devinfo,
1574 const struct brw_cs_prog_data *cs_prog_data,
1575 unsigned group_size);
1576
1577 void
1578 brw_write_shader_relocs(const struct gen_device_info *devinfo,
1579 void *program,
1580 const struct brw_stage_prog_data *prog_data,
1581 struct brw_shader_reloc_value *values,
1582 unsigned num_values);
1583
1584 /**
1585 * Calculate the RightExecutionMask field used in GPGPU_WALKER.
1586 */
1587 static inline unsigned
brw_cs_right_mask(unsigned group_size,unsigned simd_size)1588 brw_cs_right_mask(unsigned group_size, unsigned simd_size)
1589 {
1590 const uint32_t remainder = group_size & (simd_size - 1);
1591 if (remainder > 0)
1592 return ~0u >> (32 - remainder);
1593 else
1594 return ~0u >> (32 - simd_size);
1595 }
1596
1597 /**
1598 * Return true if the given shader stage is dispatched contiguously by the
1599 * relevant fixed function starting from channel 0 of the SIMD thread, which
1600 * implies that the dispatch mask of a thread can be assumed to have the form
1601 * '2^n - 1' for some n.
1602 */
1603 static inline bool
brw_stage_has_packed_dispatch(ASSERTED const struct gen_device_info * devinfo,gl_shader_stage stage,const struct brw_stage_prog_data * prog_data)1604 brw_stage_has_packed_dispatch(ASSERTED const struct gen_device_info *devinfo,
1605 gl_shader_stage stage,
1606 const struct brw_stage_prog_data *prog_data)
1607 {
1608 /* The code below makes assumptions about the hardware's thread dispatch
1609 * behavior that could be proven wrong in future generations -- Make sure
1610 * to do a full test run with brw_fs_test_dispatch_packing() hooked up to
1611 * the NIR front-end before changing this assertion.
1612 */
1613 assert(devinfo->gen <= 12);
1614
1615 switch (stage) {
1616 case MESA_SHADER_FRAGMENT: {
1617 /* The PSD discards subspans coming in with no lit samples, which in the
1618 * per-pixel shading case implies that each subspan will either be fully
1619 * lit (due to the VMask being used to allow derivative computations),
1620 * or not dispatched at all. In per-sample dispatch mode individual
1621 * samples from the same subspan have a fixed relative location within
1622 * the SIMD thread, so dispatch of unlit samples cannot be avoided in
1623 * general and we should return false.
1624 */
1625 const struct brw_wm_prog_data *wm_prog_data =
1626 (const struct brw_wm_prog_data *)prog_data;
1627 return !wm_prog_data->persample_dispatch;
1628 }
1629 case MESA_SHADER_COMPUTE:
1630 /* Compute shaders will be spawned with either a fully enabled dispatch
1631 * mask or with whatever bottom/right execution mask was given to the
1632 * GPGPU walker command to be used along the workgroup edges -- In both
1633 * cases the dispatch mask is required to be tightly packed for our
1634 * invocation index calculations to work.
1635 */
1636 return true;
1637 default:
1638 /* Most remaining fixed functions are limited to use a packed dispatch
1639 * mask due to the hardware representation of the dispatch mask as a
1640 * single counter representing the number of enabled channels.
1641 */
1642 return true;
1643 }
1644 }
1645
1646 /**
1647 * Computes the first varying slot in the URB produced by the previous stage
1648 * that is used in the next stage. We do this by testing the varying slots in
1649 * the previous stage's vue map against the inputs read in the next stage.
1650 *
1651 * Note that:
1652 *
1653 * - Each URB offset contains two varying slots and we can only skip a
1654 * full offset if both slots are unused, so the value we return here is always
1655 * rounded down to the closest multiple of two.
1656 *
1657 * - gl_Layer and gl_ViewportIndex don't have their own varying slots, they are
1658 * part of the vue header, so if these are read we can't skip anything.
1659 */
1660 static inline int
brw_compute_first_urb_slot_required(uint64_t inputs_read,const struct brw_vue_map * prev_stage_vue_map)1661 brw_compute_first_urb_slot_required(uint64_t inputs_read,
1662 const struct brw_vue_map *prev_stage_vue_map)
1663 {
1664 if ((inputs_read & (VARYING_BIT_LAYER | VARYING_BIT_VIEWPORT)) == 0) {
1665 for (int i = 0; i < prev_stage_vue_map->num_slots; i++) {
1666 int varying = prev_stage_vue_map->slot_to_varying[i];
1667 if (varying > 0 && (inputs_read & BITFIELD64_BIT(varying)) != 0)
1668 return ROUND_DOWN_TO(i, 2);
1669 }
1670 }
1671
1672 return 0;
1673 }
1674
1675 #ifdef __cplusplus
1676 } /* extern "C" */
1677 #endif
1678
1679 #endif /* BRW_COMPILER_H */
1680