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Searched refs:BRW_COMPUTE_PIPELINE (Results 1 – 6 of 6) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_state_upload.c272 case BRW_COMPUTE_PIPELINE: in brw_get_pipeline_atoms()
581 } else if (pipeline == BRW_COMPUTE_PIPELINE) { in brw_upload_programs()
783 brw_upload_pipeline_state(brw, BRW_COMPUTE_PIPELINE); in brw_upload_compute_state()
789 brw_pipeline_state_finished(brw, BRW_COMPUTE_PIPELINE); in brw_compute_state_finished()
Dbrw_program_cache.c428 brw->state.pipelines[BRW_COMPUTE_PIPELINE].mesa = ~0; in brw_clear_cache()
429 brw->state.pipelines[BRW_COMPUTE_PIPELINE].brw = ~0ull; in brw_clear_cache()
DgenX_pipe_control.c63 (GEN_GEN >= 7 && brw->last_pipeline == BRW_COMPUTE_PIPELINE)
Dbrw_misc_state.c486 if (pipeline == BRW_COMPUTE_PIPELINE) { in brw_emit_select_pipeline()
561 (pipeline == BRW_COMPUTE_PIPELINE ? 2 : 0)); in brw_emit_select_pipeline()
Dbrw_context.h154 BRW_COMPUTE_PIPELINE, enumerator
DgenX_state_upload.c5921 brw_copy_pipeline_atoms(brw, BRW_COMPUTE_PIPELINE,