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Searched refs:BRW_MASK_DISABLE (Results 1 – 10 of 10) sorted by relevance

/external/mesa3d/src/intel/compiler/
Dbrw_vec4_generator.cpp224 brw_set_default_mask_control(p, BRW_MASK_DISABLE); in generate_tex()
304 brw_set_default_mask_control(p, BRW_MASK_DISABLE); in generate_tex()
392 brw_set_default_mask_control(p, BRW_MASK_DISABLE); in generate_gs_urb_write_allocate()
439 brw_set_default_mask_control(p, BRW_MASK_DISABLE); in generate_gs_set_write_offset()
463 brw_set_default_mask_control(p, BRW_MASK_DISABLE); in generate_gs_set_vertex_count()
537 brw_set_default_mask_control(p, BRW_MASK_DISABLE); in generate_gs_svb_set_destination_index()
549 brw_set_default_mask_control(p, BRW_MASK_DISABLE); in generate_gs_set_dword_2()
567 brw_set_default_mask_control(p, BRW_MASK_DISABLE); in generate_gs_prepare_channel_masks()
631 brw_set_default_mask_control(p, BRW_MASK_DISABLE); in generate_gs_set_channel_masks()
695 brw_set_default_mask_control(p, BRW_MASK_DISABLE); in generate_gs_ff_sync()
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Dbrw_compile_clip.c60 brw_set_default_mask_control(&c.func, BRW_MASK_DISABLE); in brw_compile_clip()
Dbrw_eu_emit.c61 brw_set_default_mask_control(p, BRW_MASK_DISABLE); in gen6_resolve_implied_move()
1336 brw_inst_set_mask_control(devinfo, inst, BRW_MASK_DISABLE); in brw_JMPI()
2127 brw_set_default_mask_control(p, BRW_MASK_DISABLE); in brw_oword_block_write_scratch()
2248 brw_set_default_mask_control(p, BRW_MASK_DISABLE); in brw_oword_block_read_scratch()
2346 brw_set_default_mask_control(p, BRW_MASK_DISABLE); in brw_oword_block_read()
2605 brw_set_default_mask_control(p, BRW_MASK_DISABLE); in brw_urb_WRITE()
2660 brw_set_default_mask_control(p, BRW_MASK_DISABLE); in brw_send_indirect_message()
2715 brw_set_default_mask_control(p, BRW_MASK_DISABLE); in brw_send_indirect_split_message()
2741 brw_set_default_mask_control(p, BRW_MASK_DISABLE); in brw_send_indirect_split_message()
2818 brw_set_default_mask_control(p, BRW_MASK_DISABLE); in brw_send_indirect_surface_message()
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Dbrw_fs_generator.cpp277 brw_inst_set_mask_control(devinfo, reset, BRW_MASK_DISABLE); in patch_discard_jumps_to_fb_writes()
302 brw_set_default_mask_control(p, BRW_MASK_DISABLE); in patch_discard_jumps_to_fb_writes()
365 brw_set_default_mask_control(p, BRW_MASK_DISABLE); in fire_fb_write()
536 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE); in generate_mov_indirect()
682 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE); in generate_shuffle()
897 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE); in generate_cs_terminate()
1250 brw_set_default_mask_control(p, BRW_MASK_DISABLE); in generate_tex()
1626 brw_set_default_mask_control(p, BRW_MASK_DISABLE); in generate_uniform_pull_constant_load_gen7()
1646 brw_set_default_mask_control(p, BRW_MASK_DISABLE); in generate_uniform_pull_constant_load_gen7()
1937 brw_set_default_mask_control(p, BRW_MASK_DISABLE); in generate_code()
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Dbrw_eu_defines.h176 #define BRW_MASK_DISABLE 1 macro
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_ff_gs.c73 brw_set_default_mask_control(&c.func, BRW_MASK_DISABLE); in brw_codegen_ff_gs_prog()
/external/igt-gpu-tools/assembler/
Dbrw_eu_emit.c76 brw_set_mask_control(p, BRW_MASK_DISABLE); in gen6_resolve_implied_move()
1110 insn->header.mask_control = BRW_MASK_DISABLE; in brw_JMPI()
1922 brw_set_mask_control(p, BRW_MASK_DISABLE); in brw_oword_block_write_scratch()
2031 brw_set_mask_control(p, BRW_MASK_DISABLE); in brw_oword_block_read_scratch()
2093 brw_set_mask_control(p, BRW_MASK_DISABLE); in brw_oword_block_read()
2259 brw_set_mask_control(p, BRW_MASK_DISABLE); in brw_SAMPLE()
2602 brw_set_mask_control(p, BRW_MASK_DISABLE); in brw_shader_time_add()
Dbrw_defines.h609 #define BRW_MASK_DISABLE 1 macro
Dgram.y608 options->mask_control = BRW_MASK_DISABLE; in add_option()
1450 gen8_set_mask_control(GEN8(&$$), BRW_MASK_DISABLE);
1452 GEN(&$$)->header.mask_control = BRW_MASK_DISABLE;
/external/mesa3d/src/intel/tools/
Di965_gram.y564 options->mask_control |= BRW_MASK_DISABLE; in add_instruction_option()
925 brw_inst_set_mask_control(p->devinfo, brw_last_inst, BRW_MASK_DISABLE);