Searched refs:BRW_OPCODE_F32TO16 (Results 1 – 13 of 13) sorted by relevance
| /external/mesa3d/src/intel/compiler/ |
| D | brw_shader.cpp | 177 if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16) in brw_instruction_name()
965 case BRW_OPCODE_F32TO16: in can_do_saturate()
1013 case BRW_OPCODE_F32TO16: in can_do_cmod()
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| D | brw_eu_defines.h | 220 BRW_OPCODE_F32TO16, /**< Gen7 only */ enumerator
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| D | brw_eu.cpp | 628 { BRW_OPCODE_F32TO16, 19, "f32to16", 1, 1, GEN7 | GEN75 },
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| D | brw_ir_performance.cpp | 464 case BRW_OPCODE_F32TO16: in instruction_desc()
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| D | brw_vec4_generator.cpp | 1617 case BRW_OPCODE_F32TO16: in generate_code()
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| D | brw_fs_generator.cpp | 2096 case BRW_OPCODE_F32TO16: in generate_code()
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| D | brw_eu_emit.c | 1261 inst = brw_alu1(p, BRW_OPCODE_F32TO16, dst, src); in brw_F32TO16()
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| D | brw_fs.cpp | 6220 if (inst->opcode == BRW_OPCODE_F32TO16 && in is_mixed_float_with_packed_fp16_dst()
6526 case BRW_OPCODE_F32TO16: in get_lowered_simd_width()
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| D | brw_fs_nir.cpp | 1646 bld.emit(BRW_OPCODE_F32TO16, tmp16, op[0]); in nir_emit_alu()
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| /external/igt-gpu-tools/assembler/ |
| D | lex.l | 98 "f32to16" { yylval.integer = BRW_OPCODE_F32TO16; return F32TO16; }
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| D | brw_defines.h | 650 BRW_OPCODE_F32TO16 = 19, enumerator
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| /external/mesa3d/src/intel/tools/ |
| D | i965_lex.l | 81 f32to16 { yylval.integer = BRW_OPCODE_F32TO16; return F32TO16; }
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| D | i965_gram.y | 110 case BRW_OPCODE_F32TO16: in i965_asm_unary_instruction()
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