Searched refs:BRW_SWIZZLE_XYZW (Results 1 – 13 of 13) sorted by relevance
| /external/mesa3d/src/intel/compiler/ |
| D | brw_reg.h | 79 #define BRW_SWIZZLE_XYZW BRW_SWIZZLE4(0,1,2,3) macro
97 #define BRW_SWZ_COMP_INPUT(comp) (BRW_SWIZZLE_XYZW >> ((comp)*2))
98 #define BRW_SWZ_COMP_OUTPUT(comp) (BRW_SWIZZLE_XYZW << ((comp)*2))
463 BRW_SWIZZLE_XYZW, in brw_vec16_reg()
480 BRW_SWIZZLE_XYZW, in brw_vec8_reg()
497 BRW_SWIZZLE_XYZW, in brw_vec4_reg()
866 BRW_SWIZZLE_XYZW, /* NOTE! */ in brw_ip_reg()
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| D | brw_vec4_copy_propagation.cpp | 105 src.swizzle = BRW_SWIZZLE_XYZW; in get_copy_value()
353 value.swizzle != BRW_SWIZZLE_XYZW) && !inst->can_do_source_mods(devinfo)) in try_copy_propagate()
373 if (is_align1_opcode(inst->opcode) && composed_swizzle != BRW_SWIZZLE_XYZW) in try_copy_propagate()
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| D | brw_vec4_tcs.cpp | 294 unsigned swiz = BRW_SWIZZLE_XYZW; in nir_emit_intrinsic()
301 assert(swiz == BRW_SWIZZLE_XYZW); in nir_emit_intrinsic()
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| D | test_vec4_register_coalesce.cpp | 164 src.swizzle = BRW_SWIZZLE_XYZW; in TEST_F()
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| D | brw_vec4_cmod_propagation.cpp | 45 later->src[0].swizzle != BRW_SWIZZLE_XYZW) || in writemasks_incompatible()
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| D | brw_vec4_reg_allocate.cpp | 526 temp.swizzle = BRW_SWIZZLE_XYZW; in spill_reg()
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| D | brw_vec4.cpp | 58 this->swizzle = BRW_SWIZZLE_XYZW; in src_reg()
1135 if (devinfo->gen == 6 && is_math() && swizzle != BRW_SWIZZLE_XYZW) in can_reswizzle()
1904 BRW_SWIZZLE_XYZW, in get_timestamp()
2427 case BRW_SWIZZLE_XYZW: in is_supported_64bit_region()
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| D | brw_fs_copy_propagation.cpp | 637 assert(entry->src.swizzle == BRW_SWIZZLE_XYZW); in try_copy_propagate()
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| D | brw_disasm.c | 964 } else if (swiz != BRW_SWIZZLE_XYZW) { in src_swizzle()
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| D | brw_vec4_nir.cpp | 2162 if (src.swizzle != BRW_SWIZZLE_XYZW) { in shuffle_64bit_data()
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| D | brw_vec4_generator.cpp | 51 assert(src.swizzle == BRW_SWIZZLE_XYZW); in check_gen6_math_src_arg()
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| D | brw_fs.cpp | 3335 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW); in emit_repclear_shader()
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| /external/igt-gpu-tools/assembler/ |
| D | brw_reg.h | 74 #define BRW_SWIZZLE_XYZW BRW_SWIZZLE4(0,1,2,3) macro
234 BRW_SWIZZLE_XYZW, in brw_vec16_reg()
249 BRW_SWIZZLE_XYZW, in brw_vec8_reg()
264 BRW_SWIZZLE_XYZW, in brw_vec4_reg()
539 BRW_SWIZZLE_XYZW, /* NOTE! */ in brw_ip_reg()
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