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Searched refs:BRW_VERTICAL_STRIDE_0 (Results 1 – 14 of 14) sorted by relevance

/external/igt-gpu-tools/assembler/
Dbrw_reg.h291 BRW_VERTICAL_STRIDE_0, in brw_vec1_reg()
368 BRW_VERTICAL_STRIDE_0, in brw_imm_reg()
429 imm.vstride = BRW_VERTICAL_STRIDE_0; in brw_imm_v()
441 imm.vstride = BRW_VERTICAL_STRIDE_0; in brw_imm_vf()
456 imm.vstride = BRW_VERTICAL_STRIDE_0; in brw_imm_vf4()
557 BRW_VERTICAL_STRIDE_0, in brw_notification_1_reg()
Dgen8_instruction.c195 gen8_set_src0_vert_stride(inst, BRW_VERTICAL_STRIDE_0); in gen8_set_src0()
233 gen8_set_src0_vert_stride(inst, BRW_VERTICAL_STRIDE_0); in gen8_set_src0()
284 gen8_set_src1_vert_stride(inst, BRW_VERTICAL_STRIDE_0); in gen8_set_src1()
321 gen8_set_src1_vert_stride(inst, BRW_VERTICAL_STRIDE_0); in gen8_set_src1()
Dbrw_eu_debug.c69 hwreg.vstride == BRW_VERTICAL_STRIDE_0 && in brw_print_reg()
Dbrw_eu_emit.c808 if (reg.vstride == BRW_VERTICAL_STRIDE_0) { in get_3src_subreg_nr()
866 insn->bits2.da3src.src0_rep_ctrl = src0.vstride == BRW_VERTICAL_STRIDE_0; in brw_set_3src_src0()
881 insn->bits2.da3src.src1_rep_ctrl = src1.vstride == BRW_VERTICAL_STRIDE_0; in brw_set_3src_src1()
898 insn->bits3.da3src.src2_rep_ctrl = src2.vstride == BRW_VERTICAL_STRIDE_0; in brw_set_3src_src2()
Dbrw_defines.h820 #define BRW_VERTICAL_STRIDE_0 0 macro
/external/mesa3d/src/intel/compiler/
Dbrw_reg.h528 BRW_VERTICAL_STRIDE_0, in brw_vec1_reg()
635 BRW_VERTICAL_STRIDE_0, in brw_imm_reg()
756 imm.vstride = BRW_VERTICAL_STRIDE_0; in brw_imm_vf4()
879 BRW_VERTICAL_STRIDE_0, in brw_notification_reg()
1240 region_matches(reg, BRW_VERTICAL_STRIDE_0, BRW_WIDTH_1, \
Dbrw_disasm.c1019 case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0: return BRW_VERTICAL_STRIDE_0; in vstride_from_align1_3src_vstride()
1049 case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0: return BRW_VERTICAL_STRIDE_0; in vstride_from_align1_3src_hstride()
1066 if (_vert_stride == BRW_VERTICAL_STRIDE_0 && in implied_width()
1076 case BRW_VERTICAL_STRIDE_0: in implied_width()
1154 _vert_stride = BRW_VERTICAL_STRIDE_0; in src0_3src()
1163 is_scalar_region = _vert_stride == BRW_VERTICAL_STRIDE_0 && in src0_3src()
1227 _vert_stride = BRW_VERTICAL_STRIDE_0; in src1_3src()
1236 is_scalar_region = _vert_stride == BRW_VERTICAL_STRIDE_0 && in src1_3src()
1314 _vert_stride = BRW_VERTICAL_STRIDE_0; in src2_3src()
1323 is_scalar_region = _vert_stride == BRW_VERTICAL_STRIDE_0 && in src2_3src()
Dbrw_eu_validate.c203 return brw_inst_src0_vstride(devinfo, inst) == BRW_VERTICAL_STRIDE_0 && in src0_has_scalar_region()
211 return brw_inst_src1_vstride(devinfo, inst) == BRW_VERTICAL_STRIDE_0 && in src1_has_scalar_region()
948 brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_0 && in general_restrictions_on_region_parameters()
954 brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_0 && in general_restrictions_on_region_parameters()
963 brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_0 && in general_restrictions_on_region_parameters()
969 brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_0 && in general_restrictions_on_region_parameters()
Dbrw_eu_emit.c303 brw_inst_set_src0_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_0); in brw_set_src0()
410 brw_inst_set_src1_vstride(devinfo, inst, BRW_VERTICAL_STRIDE_0); in brw_set_src1()
749 case BRW_VERTICAL_STRIDE_0: in to_3src_align1_vstride()
946 src0.vstride == BRW_VERTICAL_STRIDE_0); in brw_alu3()
955 src1.vstride == BRW_VERTICAL_STRIDE_0); in brw_alu3()
964 src2.vstride == BRW_VERTICAL_STRIDE_0); in brw_alu3()
1026 if (src0.vstride == BRW_VERTICAL_STRIDE_0) \
1028 if (src1.vstride == BRW_VERTICAL_STRIDE_0) \
1030 if (src2.vstride == BRW_VERTICAL_STRIDE_0) \
1056 if (src0.vstride == BRW_VERTICAL_STRIDE_0) \
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Dtest_eu_validate.cpp217 brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0); in TEST_P()
681 brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0); in TEST_P()
690 brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0); in TEST_P()
727 brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0); in TEST_P()
736 brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0); in TEST_P()
834 { BRW_VERTICAL_STRIDE_0, true }, in TEST_P()
1127 brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0); in TEST_P()
1144 brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0); in TEST_P()
Dbrw_vec4.cpp1901 BRW_VERTICAL_STRIDE_0, in get_timestamp()
2102 if (inst->src[i].vstride == BRW_VERTICAL_STRIDE_0 && in convert_to_hw_regs()
2628 hw_reg->vstride = BRW_VERTICAL_STRIDE_0; in apply_logical_swizzle()
2639 hw_reg->vstride = BRW_VERTICAL_STRIDE_0; in apply_logical_swizzle()
Dbrw_eu_defines.h1021 BRW_VERTICAL_STRIDE_0 = 0, enumerator
Dbrw_fs_generator.cpp176 brw_reg.vstride == BRW_VERTICAL_STRIDE_0 && in brw_reg_from_fs_reg()
1848 value.vstride = BRW_VERTICAL_STRIDE_0; in generate_shader_time_add()
Dbrw_vec4_generator.cpp935 if (offset.vstride == BRW_VERTICAL_STRIDE_0 && in generate_tes_add_indirect_urb_offset()