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Searched refs:BRW_WIDTH_1 (Results 1 – 14 of 14) sorted by relevance

/external/igt-gpu-tools/assembler/
Dgen8_instruction.c192 if (reg.width == BRW_WIDTH_1 && in gen8_set_src0()
230 if (reg.width == BRW_WIDTH_1 && in gen8_set_src0()
281 if (reg.width == BRW_WIDTH_1 && in gen8_set_src1()
318 if (reg.width == BRW_WIDTH_1 && in gen8_set_src1()
Dbrw_reg.h292 BRW_WIDTH_1, in brw_vec1_reg()
369 BRW_WIDTH_1, in brw_imm_reg()
537 BRW_WIDTH_1, in brw_ip_reg()
558 BRW_WIDTH_1, in brw_notification_1_reg()
Dbrw_eu_debug.c70 hwreg.width == BRW_WIDTH_1 && in brw_print_reg()
Dgram.y663 $$.width = BRW_WIDTH_1;
1455 ip_dst.width = BRW_WIDTH_1;
1516 notify_dst.width = BRW_WIDTH_1;
2711 $$.width = BRW_WIDTH_1;
2720 $$.width = BRW_WIDTH_1;
3024 src->reg.width = BRW_WIDTH_1; in reset_instruction_src_region()
Dbrw_defines.h832 #define BRW_WIDTH_1 0 macro
/external/mesa3d/src/intel/compiler/
Dbrw_reg.h529 BRW_WIDTH_1, in brw_vec1_reg()
636 BRW_WIDTH_1, in brw_imm_reg()
864 BRW_WIDTH_1, in brw_ip_reg()
880 BRW_WIDTH_1, in brw_notification_reg()
1240 region_matches(reg, BRW_VERTICAL_STRIDE_0, BRW_WIDTH_1, \
Dbrw_disasm.c1068 return BRW_WIDTH_1; in implied_width()
1155 _width = BRW_WIDTH_1; in src0_3src()
1164 _width == BRW_WIDTH_1 && in src0_3src()
1228 _width = BRW_WIDTH_1; in src1_3src()
1237 _width == BRW_WIDTH_1 && in src1_3src()
1315 _width = BRW_WIDTH_1; in src2_3src()
1324 _width == BRW_WIDTH_1 && in src2_3src()
Dtest_eu_validate.cpp218 brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_1); in TEST_P()
682 brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_1); in TEST_P()
691 brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_1); in TEST_P()
705 brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_1); in TEST_P()
715 brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_1); in TEST_P()
1039 brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_1); in TEST_P()
1057 brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_1); in TEST_P()
1128 brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_1); in TEST_P()
1145 brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_1); in TEST_P()
Dbrw_eu_emit.c299 if (reg.width == BRW_WIDTH_1 && in brw_set_src0()
302 brw_inst_set_src0_width(devinfo, inst, BRW_WIDTH_1); in brw_set_src0()
406 if (reg.width == BRW_WIDTH_1 && in brw_set_src1()
409 brw_inst_set_src1_width(devinfo, inst, BRW_WIDTH_1); in brw_set_src1()
1209 src0.width = BRW_WIDTH_1; in brw_LINE()
1219 src0.width = BRW_WIDTH_1; in brw_PLN()
Dbrw_eu_defines.h1040 BRW_WIDTH_1 = 0, enumerator
Dbrw_eu_validate.c204 brw_inst_src0_width(devinfo, inst) == BRW_WIDTH_1 && in src0_has_scalar_region()
212 brw_inst_src1_width(devinfo, inst) == BRW_WIDTH_1 && in src1_has_scalar_region()
Dbrw_vec4_generator.cpp1919 src[0].width = BRW_WIDTH_1; in generate_code()
2047 src[0].width = BRW_WIDTH_1; in generate_code()
Dbrw_fs_generator.cpp177 brw_reg.width == BRW_WIDTH_1 && in brw_reg_from_fs_reg()
1846 value.width = BRW_WIDTH_1; in generate_shader_time_add()
/external/mesa3d/src/intel/tools/
Di965_gram.y1509 $$.width = BRW_WIDTH_1;
1535 $$.width = BRW_WIDTH_1;