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Searched refs:BRW_WIDTH_8 (Results 1 – 11 of 11) sorted by relevance

/external/igt-gpu-tools/assembler/
Dbrw_eu_debug.c62 hwreg.width == BRW_WIDTH_8 && in brw_print_reg()
Dbrw_reg.h247 BRW_WIDTH_8, in brw_vec8_reg()
430 imm.width = BRW_WIDTH_8; in brw_imm_v()
Dbrw_defines.h835 #define BRW_WIDTH_8 3 macro
Dbrw_eu_emit.c48 if (reg.width == BRW_WIDTH_8 && p->compressed) in guess_execution_size()
Dgram.y3046 src->reg.width = BRW_WIDTH_8; in reset_instruction_src_region()
/external/mesa3d/src/intel/compiler/
Dbrw_eu_defines.h1043 BRW_WIDTH_8 = 3, enumerator
Dbrw_fs_builder.h753 src.width != BRW_WIDTH_8 || in fix_3src_operand()
Dbrw_reg.h478 BRW_WIDTH_8, in brw_vec8_reg()
Dtest_eu_validate.cpp876 brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_8); in TEST_P()
889 brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_8); in TEST_P()
970 brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_8); in TEST_P()
Dbrw_disasm.c1075 case BRW_VERTICAL_STRIDE_8: return BRW_WIDTH_8; in implied_width()
Dbrw_eu_emit.c1222 src1.width = BRW_WIDTH_8; in brw_PLN()