| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FixupLEAs.cpp | 368 Register BaseReg = Base.getReg(); in optTwoAddrLEA() local
377 if (BaseReg != 0) in optTwoAddrLEA()
378 BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit); in optTwoAddrLEA()
387 if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 && in optTwoAddrLEA()
388 (DestReg == BaseReg || DestReg == IndexReg)) { in optTwoAddrLEA()
390 if (DestReg != BaseReg) in optTwoAddrLEA()
391 std::swap(BaseReg, IndexReg); in optTwoAddrLEA()
396 .addReg(BaseReg).addReg(IndexReg) in optTwoAddrLEA()
401 .addReg(BaseReg).addReg(IndexReg); in optTwoAddrLEA()
403 } else if (DestReg == BaseReg && IndexReg == 0) { in optTwoAddrLEA()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86FixupLEAs.cpp | 384 Register BaseReg = Base.getReg(); in optTwoAddrLEA() local
393 if (BaseReg != 0) in optTwoAddrLEA()
394 BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit); in optTwoAddrLEA()
403 if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 && in optTwoAddrLEA()
404 (DestReg == BaseReg || DestReg == IndexReg)) { in optTwoAddrLEA()
406 if (DestReg != BaseReg) in optTwoAddrLEA()
407 std::swap(BaseReg, IndexReg); in optTwoAddrLEA()
412 .addReg(BaseReg).addReg(IndexReg) in optTwoAddrLEA()
417 .addReg(BaseReg).addReg(IndexReg); in optTwoAddrLEA()
419 } else if (DestReg == BaseReg && IndexReg == 0) { in optTwoAddrLEA()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIFixupVectorISel.cpp | 86 unsigned &BaseReg, in findSRegBaseAndIndex() argument
115 BaseReg = DefInst->getOperand(2).getReg(); in findSRegBaseAndIndex()
132 MI = MRI.getUniqueVRegDef(BaseReg); in findSRegBaseAndIndex()
136 BaseReg = MI->getOperand(1).getReg(); in findSRegBaseAndIndex()
137 BaseRC = MRI.getRegClass(BaseReg); in findSRegBaseAndIndex()
141 if (!TRI->isSGPRReg(MRI, BaseReg)) in findSRegBaseAndIndex()
147 MRI.clearKillFlags(BaseReg); in findSRegBaseAndIndex()
175 unsigned BaseReg = 0; in fixupGlobalSaddr() local
178 if (!findSRegBaseAndIndex(Op, BaseReg, IndexReg, MRI, TRI)) in fixupGlobalSaddr()
192 NewGlob->addOperand(MF, MachineOperand::CreateReg(BaseReg, false)); in fixupGlobalSaddr()
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| /external/llvm-project/llvm/lib/Target/ARC/ |
| D | ARCRegisterInfo.cpp | 46 unsigned BaseReg = FrameReg; in ReplaceFrameIndex() local
51 .addReg(BaseReg) in ReplaceFrameIndex()
60 BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass); in ReplaceFrameIndex()
61 if (!BaseReg) { in ReplaceFrameIndex()
66 BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj); in ReplaceFrameIndex()
67 assert(BaseReg && "Register scavenging failed."); in ReplaceFrameIndex()
68 LLVM_DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI) in ReplaceFrameIndex()
72 RS->setRegUsed(BaseReg); in ReplaceFrameIndex()
76 .addReg(BaseReg, RegState::Define) in ReplaceFrameIndex()
94 .addReg(BaseReg, KillState) in ReplaceFrameIndex()
[all …]
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| D | ARCOptAddrMode.cpp | 90 MachineOperand &Incr, unsigned BaseReg);
94 void fixPastUses(ArrayRef<MachineInstr *> Uses, unsigned BaseReg,
287 Register BaseReg = Ldst->getOperand(BasePos).getReg(); in canJoinInstructions() local
297 if (Add->getOperand(0).getReg() == StReg || BaseReg == StReg) { in canJoinInstructions()
305 for (MachineInstr &MI : MRI->use_nodbg_instructions(BaseReg)) { in canJoinInstructions()
343 MachineOperand &Incr, unsigned BaseReg) { in canFixPastUses() argument
449 Register BaseReg = Ldst.getOperand(BasePos).getReg(); in changeToAddrMode() local
463 Ldst.addOperand(MachineOperand::CreateReg(BaseReg, false)); in changeToAddrMode()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| D | ARCRegisterInfo.cpp | 46 unsigned BaseReg = FrameReg; in ReplaceFrameIndex() local
51 .addReg(BaseReg) in ReplaceFrameIndex()
60 BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass); in ReplaceFrameIndex()
61 if (!BaseReg) { in ReplaceFrameIndex()
66 BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj); in ReplaceFrameIndex()
67 assert(BaseReg && "Register scavenging failed."); in ReplaceFrameIndex()
68 LLVM_DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI) in ReplaceFrameIndex()
72 RS->setRegUsed(BaseReg); in ReplaceFrameIndex()
76 .addReg(BaseReg, RegState::Define) in ReplaceFrameIndex()
94 .addReg(BaseReg, KillState) in ReplaceFrameIndex()
[all …]
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| D | ARCOptAddrMode.cpp | 90 MachineOperand &Incr, unsigned BaseReg);
94 void fixPastUses(ArrayRef<MachineInstr *> Uses, unsigned BaseReg,
287 Register BaseReg = Ldst->getOperand(BasePos).getReg(); in canJoinInstructions() local
297 if (Add->getOperand(0).getReg() == StReg || BaseReg == StReg) { in canJoinInstructions()
305 for (MachineInstr &MI : MRI->use_nodbg_instructions(BaseReg)) { in canJoinInstructions()
343 MachineOperand &Incr, unsigned BaseReg) { in canFixPastUses() argument
449 Register BaseReg = Ldst.getOperand(BasePos).getReg(); in changeToAddrMode() local
463 Ldst.addOperand(MachineOperand::CreateReg(BaseReg, false)); in changeToAddrMode()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ThumbRegisterInfo.cpp | 126 const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, in emitThumbRegPlusImmInReg() argument
132 (BaseReg != 0 && !isARMLowRegister(BaseReg)); in emitThumbRegPlusImmInReg()
144 assert(BaseReg == ARM::SP && "Unexpected!"); in emitThumbRegPlusImmInReg()
176 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); in emitThumbRegPlusImmInReg()
178 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmInReg()
189 unsigned BaseReg, int NumBytes, in emitThumbRegPlusImmediate() argument
220 if (BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
232 if (BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
238 } else if (DestReg == BaseReg) { in emitThumbRegPlusImmediate()
241 } else if (isARMLowRegister(BaseReg)) { in emitThumbRegPlusImmediate()
[all …]
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| D | Thumb2InstrInfo.cpp | 233 unsigned BaseReg, int NumBytes, in emitT2RegPlusImmediate() argument
237 if (NumBytes == 0 && DestReg != BaseReg) { in emitT2RegPlusImmediate()
239 .addReg(BaseReg, RegState::Kill) in emitT2RegPlusImmediate()
249 if (DestReg != ARM::SP && DestReg != BaseReg && in emitT2RegPlusImmediate()
271 .addReg(BaseReg) in emitT2RegPlusImmediate()
283 .addReg(BaseReg) in emitT2RegPlusImmediate()
296 if (DestReg == ARM::SP && BaseReg != ARM::SP) { in emitT2RegPlusImmediate()
299 .addReg(BaseReg) in emitT2RegPlusImmediate()
302 BaseReg = ARM::SP; in emitT2RegPlusImmediate()
306 assert((DestReg != ARM::SP || BaseReg == ARM::SP) && in emitT2RegPlusImmediate()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ThumbRegisterInfo.cpp | 125 const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, in emitThumbRegPlusImmInReg() argument
131 (BaseReg != 0 && !isARMLowRegister(BaseReg)); in emitThumbRegPlusImmInReg()
143 assert(BaseReg == ARM::SP && "Unexpected!"); in emitThumbRegPlusImmInReg()
175 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); in emitThumbRegPlusImmInReg()
177 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmInReg()
188 Register BaseReg, int NumBytes, in emitThumbRegPlusImmediate() argument
219 if (BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
231 if (BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
237 } else if (DestReg == BaseReg) { in emitThumbRegPlusImmediate()
240 } else if (isARMLowRegister(BaseReg)) { in emitThumbRegPlusImmediate()
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| /external/llvm/lib/Target/ARM/ |
| D | ThumbRegisterInfo.cpp | 125 const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, in emitThumbRegPlusImmInReg() argument
130 (BaseReg != 0 && !isARMLowRegister(BaseReg)); in emitThumbRegPlusImmInReg()
142 assert(BaseReg == ARM::SP && "Unexpected!"); in emitThumbRegPlusImmInReg()
168 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); in emitThumbRegPlusImmInReg()
170 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmInReg()
181 unsigned BaseReg, int NumBytes, in emitThumbRegPlusImmediate() argument
212 if (BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
224 if (BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
230 } else if (DestReg == BaseReg) { in emitThumbRegPlusImmediate()
233 } else if (isARMLowRegister(BaseReg)) { in emitThumbRegPlusImmediate()
[all …]
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| D | Thumb2InstrInfo.cpp | 224 unsigned BaseReg, int NumBytes, in emitT2RegPlusImmediate() argument
228 if (NumBytes == 0 && DestReg != BaseReg) { in emitT2RegPlusImmediate()
230 .addReg(BaseReg, RegState::Kill) in emitT2RegPlusImmediate()
240 if (DestReg != ARM::SP && DestReg != BaseReg && in emitT2RegPlusImmediate()
262 .addReg(BaseReg) in emitT2RegPlusImmediate()
273 .addReg(BaseReg) in emitT2RegPlusImmediate()
285 if (DestReg == ARM::SP && BaseReg != ARM::SP) { in emitT2RegPlusImmediate()
288 .addReg(BaseReg).setMIFlags(MIFlags)); in emitT2RegPlusImmediate()
289 BaseReg = ARM::SP; in emitT2RegPlusImmediate()
294 if (BaseReg == ARM::SP) { in emitT2RegPlusImmediate()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | LocalStackSlotAllocation.cpp | 269 lookupCandidateBaseReg(unsigned BaseReg, in lookupCandidateBaseReg() argument
278 return TRI->isFrameOffsetLegal(&MI, BaseReg, Offset); in lookupCandidateBaseReg()
343 unsigned BaseReg = 0; in insertFrameReferenceRegisters() local
387 lookupCandidateBaseReg(BaseReg, BaseOffset, FrameSizeAdjust, in insertFrameReferenceRegisters()
389 LLVM_DEBUG(dbgs() << " Reusing base register " << BaseReg << "\n"); in insertFrameReferenceRegisters()
406 BaseReg, BaseOffset, FrameSizeAdjust, in insertFrameReferenceRegisters()
415 BaseReg = Fn.getRegInfo().createVirtualRegister(RC); in insertFrameReferenceRegisters()
417 LLVM_DEBUG(dbgs() << " Materializing base register " << BaseReg in insertFrameReferenceRegisters()
424 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx, in insertFrameReferenceRegisters()
435 assert(BaseReg != 0 && "Unable to allocate virtual base register!"); in insertFrameReferenceRegisters()
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| /external/llvm/lib/CodeGen/ |
| D | LocalStackSlotAllocation.cpp | 255 lookupCandidateBaseReg(unsigned BaseReg, in lookupCandidateBaseReg() argument
264 return TRI->isFrameOffsetLegal(&MI, BaseReg, Offset); in lookupCandidateBaseReg()
326 unsigned BaseReg = 0; in insertFrameReferenceRegisters() local
362 lookupCandidateBaseReg(BaseReg, BaseOffset, FrameSizeAdjust, in insertFrameReferenceRegisters()
364 DEBUG(dbgs() << " Reusing base register " << BaseReg << "\n"); in insertFrameReferenceRegisters()
381 BaseReg, BaseOffset, FrameSizeAdjust, in insertFrameReferenceRegisters()
390 BaseReg = Fn.getRegInfo().createVirtualRegister(RC); in insertFrameReferenceRegisters()
392 DEBUG(dbgs() << " Materializing base register " << BaseReg << in insertFrameReferenceRegisters()
398 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx, in insertFrameReferenceRegisters()
409 assert(BaseReg != 0 && "Unable to allocate virtual base register!"); in insertFrameReferenceRegisters()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | LocalStackSlotAllocation.cpp | 271 lookupCandidateBaseReg(unsigned BaseReg, in lookupCandidateBaseReg() argument
280 return TRI->isFrameOffsetLegal(&MI, BaseReg, Offset); in lookupCandidateBaseReg()
345 unsigned BaseReg = 0; in insertFrameReferenceRegisters() local
389 lookupCandidateBaseReg(BaseReg, BaseOffset, FrameSizeAdjust, in insertFrameReferenceRegisters()
391 LLVM_DEBUG(dbgs() << " Reusing base register " << BaseReg << "\n"); in insertFrameReferenceRegisters()
408 BaseReg, BaseOffset, FrameSizeAdjust, in insertFrameReferenceRegisters()
417 BaseReg = Fn.getRegInfo().createVirtualRegister(RC); in insertFrameReferenceRegisters()
419 LLVM_DEBUG(dbgs() << " Materializing base register " << BaseReg in insertFrameReferenceRegisters()
426 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx, in insertFrameReferenceRegisters()
437 assert(BaseReg != 0 && "Unable to allocate virtual base register!"); in insertFrameReferenceRegisters()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 345 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anon7e5fbfb70111::X86AsmParser::IntelExprStateMachine
368 : State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), in IntelExprStateMachine()
377 unsigned getBaseReg() { return BaseReg; } in getBaseReg()
479 if (!BaseReg) { in onPlus()
480 BaseReg = TmpReg; in onPlus()
534 if (!BaseReg) { in onMinus()
535 BaseReg = TmpReg; in onMinus()
763 if (!BaseReg) { in onRBrac()
764 BaseReg = TmpReg; in onRBrac()
899 CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg,
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64StorePairSuppress.cpp | 146 unsigned BaseReg; in runOnMachineFunction() local
148 if (TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI)) { in runOnMachineFunction()
149 if (PrevBaseReg == BaseReg) { in runOnMachineFunction()
158 PrevBaseReg = BaseReg; in runOnMachineFunction()
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| D | AArch64RegisterInfo.h | 77 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
79 void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg,
82 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 264 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anond14900950111::X86AsmParser::IntelExprStateMachine
274 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0), in IntelExprStateMachine()
278 unsigned getBaseReg() { return BaseReg; } in getBaseReg()
384 if (!BaseReg) { in onPlus()
385 BaseReg = TmpReg; in onPlus()
421 if (!BaseReg) { in onMinus()
422 BaseReg = TmpReg; in onMinus()
600 if (!BaseReg) { in onRBrac()
601 BaseReg = TmpReg; in onRBrac()
716 CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg,
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| /external/llvm-project/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 426 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anona5c84dc30111::X86AsmParser::IntelExprStateMachine
450 : State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), in IntelExprStateMachine()
459 unsigned getBaseReg() const { return BaseReg; } in getBaseReg()
655 if (!BaseReg) { in onPlus()
656 BaseReg = TmpReg; in onPlus()
716 if (!BaseReg) { in onMinus()
717 BaseReg = TmpReg; in onMinus()
964 if (!BaseReg) { in onRBrac()
965 BaseReg = TmpReg; in onRBrac()
1122 unsigned BaseReg, unsigned IndexReg,
[all …]
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| D | X86Operand.h | 60 unsigned BaseReg; member
134 if (Mem.BaseReg) in print()
135 OS << ",BaseReg=" << X86IntelInstPrinter::getRegisterName(Mem.BaseReg); in print()
184 return Mem.BaseReg; in getMemBaseReg()
320 return isMem() && Mem.BaseReg != X86::RIP && Mem.BaseReg != X86::EIP; in isSibMem()
670 Res->Mem.BaseReg = 0;
686 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
693 assert((SegReg || BaseReg || IndexReg || DefaultBaseReg) &&
702 Res->Mem.BaseReg = BaseReg;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.h | 99 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
101 void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg,
104 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
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| D | AArch64StorePairSuppress.cpp | 154 Register BaseReg = BaseOp->getReg(); in runOnMachineFunction() local
155 if (PrevBaseReg == BaseReg) { in runOnMachineFunction()
164 PrevBaseReg = BaseReg; in runOnMachineFunction()
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 60 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is16BitMemOperand() local
64 if (is16BitMode(STI) && BaseReg.getReg() == 0 && in Is16BitMemOperand()
67 if ((BaseReg.getReg() != 0 && in Is16BitMemOperand()
68 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || in Is16BitMemOperand()
206 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is32BitMemOperand() local
209 if ((BaseReg.getReg() != 0 && in Is32BitMemOperand()
210 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || in Is32BitMemOperand()
214 if (BaseReg.getReg() == X86::EIP) { in Is32BitMemOperand()
225 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is64BitMemOperand() local
228 if ((BaseReg.getReg() != 0 && in Is64BitMemOperand()
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64LoadStoreOptimizer.cpp | 175 unsigned BaseReg, int Offset);
1163 Register BaseReg = getLdStBaseOp(LoadMI).getReg(); in findMatchingStore() local
1192 BaseReg == getLdStBaseOp(MI).getReg() && getLdStOffsetOp(MI).isImm() && in findMatchingStore()
1207 if (!ModifiedRegUnits.available(BaseReg)) in findMatchingStore()
1452 Register BaseReg = getLdStBaseOp(FirstMI).getReg(); in findMatchingInsn() local
1519 if (BaseReg == MIBaseReg && ((Offset == MIOffset + OffsetStride) || in findMatchingInsn()
1573 if (!ModifiedRegUnits.available(BaseReg)) in findMatchingInsn()
1639 if (!ModifiedRegUnits.available(BaseReg)) in findMatchingInsn()
1721 unsigned BaseReg, int Offset) { in isMatchingUpdateInsn() argument
1737 if (MI.getOperand(0).getReg() != BaseReg || in isMatchingUpdateInsn()
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