| /external/llvm/lib/CodeGen/ |
| D | IfConversion.cpp | 127 SmallVector<MachineOperand, 4> BrCond; member
455 if (!TII->ReverseBranchCondition(BBI.BrCond)) { in ReverseBranchCondition()
457 TII->InsertBranch(*BBI.BB, BBI.FalseBB, BBI.TrueBB, BBI.BrCond, dl); in ReverseBranchCondition()
517 if (TrueBBI.TrueBB && TrueBBI.BrCond.empty()) in ValidTriangle()
656 BBI.BrCond.clear(); in ScanInstructions()
658 !TII->analyzeBranch(*BBI.BB, BBI.TrueBB, BBI.FalseBB, BBI.BrCond); in ScanInstructions()
661 if (BBI.BrCond.size()) { in ScanInstructions()
779 if (BBI.BrCond.size()) { in FeasibilityAnalysis()
785 SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end()); in FeasibilityAnalysis()
832 if (!BBI.IsBrAnalyzable || BBI.BrCond.empty() || BBI.IsDone) { in AnalyzeBlock()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | IfConversion.cpp | 153 SmallVector<MachineOperand, 4> BrCond; member
626 if (!TII->reverseBranchCondition(BBI.BrCond)) { in reverseBranchCondition()
628 TII->insertBranch(*BBI.BB, BBI.FalseBB, BBI.TrueBB, BBI.BrCond, dl); in reverseBranchCondition()
689 if (TrueBBI.TrueBB && TrueBBI.BrCond.empty()) in ValidTriangle()
896 if (TrueBBI.BrCond.size() == 0 || in ValidForkedDiamond()
897 FalseBBI.BrCond.size() == 0) in ValidForkedDiamond()
1029 BBI.BrCond.clear(); in AnalyzeBranches()
1031 !TII->analyzeBranch(*BBI.BB, BBI.TrueBB, BBI.FalseBB, BBI.BrCond); in AnalyzeBranches()
1035 BBI.BrCond.clear(); in AnalyzeBranches()
1038 SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end()); in AnalyzeBranches()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | IfConversion.cpp | 152 SmallVector<MachineOperand, 4> BrCond; member
631 if (!TII->reverseBranchCondition(BBI.BrCond)) { in reverseBranchCondition()
633 TII->insertBranch(*BBI.BB, BBI.FalseBB, BBI.TrueBB, BBI.BrCond, dl); in reverseBranchCondition()
694 if (TrueBBI.TrueBB && TrueBBI.BrCond.empty()) in ValidTriangle()
901 if (TrueBBI.BrCond.size() == 0 || in ValidForkedDiamond()
902 FalseBBI.BrCond.size() == 0) in ValidForkedDiamond()
1029 BBI.BrCond.clear(); in AnalyzeBranches()
1031 !TII->analyzeBranch(*BBI.BB, BBI.TrueBB, BBI.FalseBB, BBI.BrCond); in AnalyzeBranches()
1035 BBI.BrCond.clear(); in AnalyzeBranches()
1038 SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end()); in AnalyzeBranches()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Vectorize/ |
| D | VPlanHCFGBuilder.cpp | 291 Value *BrCond = Br->getCondition(); in buildPlainCFG() local
294 assert(IRDef2VPValue.count(BrCond) && in buildPlainCFG()
296 VPValue *VPCondBit = IRDef2VPValue[BrCond]; in buildPlainCFG()
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| /external/llvm-project/llvm/lib/Transforms/Vectorize/ |
| D | VPlanHCFGBuilder.cpp | 291 Value *BrCond = Br->getCondition(); in buildPlainCFG() local
294 assert(IRDef2VPValue.count(BrCond) && in buildPlainCFG()
296 VPValue *VPCondBit = IRDef2VPValue[BrCond]; in buildPlainCFG()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceConditionCodesX8664.h | 27 enum BrCond { enum
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| D | IceConditionCodesX8632.h | 31 enum BrCond { enum
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| D | IceAssemblerX86Base.h | 58 using BrCond = typename Traits::Cond::BrCond; variable
300 void setcc(BrCond condition, ByteRegister dst);
301 void setcc(BrCond condition, const Address &address);
325 void cmov(Type Ty, BrCond cond, GPRRegister dst, GPRRegister src);
326 void cmov(Type Ty, BrCond cond, GPRRegister dst, const Address &src);
707 void j(BrCond condition, Label *label, bool near = kFarJump);
708 void j(BrCond condition, const ConstantRelocatable *label); // not testable.
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| D | IceTargetLoweringX8632Traits.h | 698 Cond::BrCond C1, C2;
709 static const struct TableIcmp32Type { Cond::BrCond Mapping; } TableIcmp32[];
719 Cond::BrCond C1, C2, C3;
724 static Cond::BrCond getIcmp32Mapping(InstIcmp::ICond Cond) {
874 Cond::BrCond Opposite;
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| D | IceTargetLoweringX86Base.h | 66 using BrCond = typename Traits::Cond::BrCond; variable
563 void _br(BrCond Condition, CfgNode *TargetTrue, CfgNode *TargetFalse) { in _br()
570 void _br(BrCond Condition, CfgNode *Target) { in _br()
573 void _br(BrCond Condition, InstX86Label *Label,
593 void _cmov(Variable *Dest, Operand *Src0, BrCond Condition) { in _cmov()
943 void _setcc(Variable *Dest, BrCond Condition) { in _setcc()
1138 void setccOrConsumer(BrCond Condition, Variable *Dest, const Inst *Consumer);
1150 void lowerSelectMove(Variable *Dest, BrCond Cond, Operand *SrcT,
1152 void lowerSelectIntMove(Variable *Dest, BrCond Cond, Operand *SrcT,
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| D | IceTargetLoweringX8664Traits.h | 792 Cond::BrCond C1, C2;
803 static const struct TableIcmp32Type { Cond::BrCond Mapping; } TableIcmp32[];
813 Cond::BrCond C1, C2, C3;
818 static Cond::BrCond getIcmp32Mapping(InstIcmp::ICond Cond) {
962 Cond::BrCond Opposite;
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| D | IceInstX86Base.h | 50 using BrCond = typename Traits::Cond::BrCond; member
207 static BrCond getOppositeCondition(BrCond Cond);
380 CfgNode *TargetFalse, BrCond Condition, in create()
397 static InstX86Br *create(Cfg *Func, CfgNode *Target, BrCond Condition, in create()
407 static InstX86Br *create(Cfg *Func, InstX86Label *Label, BrCond Condition, in create()
442 const InstX86Label *Label, BrCond Condition, Mode Kind);
444 BrCond Condition;
2474 BrCond Cond) { in create()
2486 InstX86Cmov(Cfg *Func, Variable *Dest, Operand *Source, BrCond Cond);
2488 BrCond Condition;
[all …]
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| D | IceAssemblerX86BaseImpl.h | 210 void AssemblerX86Base<TraitsType>::setcc(BrCond condition, ByteRegister dst) { in setcc()
219 void AssemblerX86Base<TraitsType>::setcc(BrCond condition, in setcc()
420 void AssemblerX86Base<TraitsType>::cmov(Type Ty, BrCond cond, GPRRegister dst, in cmov()
434 void AssemblerX86Base<TraitsType>::cmov(Type Ty, BrCond cond, GPRRegister dst, in cmov()
3587 void AssemblerX86Base<TraitsType>::j(BrCond condition, Label *label, in j()
3621 void AssemblerX86Base<TraitsType>::j(BrCond condition, in j()
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| D | IceInstX86BaseImpl.h | 44 typename InstImpl<TraitsType>::Cond::BrCond
45 InstImpl<TraitsType>::InstX86Base::getOppositeCondition(BrCond Cond) { in getOppositeCondition()
111 BrCond Condition, Mode Kind) in InstX86Br()
193 BrCond Condition) in InstX86Cmov()
366 BrCond Cond) in InstX86Setcc()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | CombinerHelper.cpp | 804 MachineInstr *BrCond = &*std::prev(BrIt); in matchElideBrByInvertingCond() local
805 if (BrCond->getOpcode() != TargetOpcode::G_BRCOND) in matchElideBrByInvertingCond()
809 if (!MBB->isLayoutSuccessor(BrCond->getOperand(1).getMBB())) in matchElideBrByInvertingCond()
812 MachineInstr *CmpMI = MRI.getVRegDef(BrCond->getOperand(0).getReg()); in matchElideBrByInvertingCond()
829 MachineInstr *BrCond = &*std::prev(BrIt); in applyElideBrByInvertingCond() local
830 MachineInstr *CmpMI = MRI.getVRegDef(BrCond->getOperand(0).getReg()); in applyElideBrByInvertingCond()
841 Observer.changingInstr(*BrCond); in applyElideBrByInvertingCond()
842 BrCond->getOperand(1).setMBB(BrTarget); in applyElideBrByInvertingCond()
843 Observer.changedInstr(*BrCond); in applyElideBrByInvertingCond()
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| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | CombinerHelper.cpp | 907 MachineInstr *BrCond = &*std::prev(BrIt); in matchOptBrCondByInvertingCond() local
908 if (BrCond->getOpcode() != TargetOpcode::G_BRCOND) in matchOptBrCondByInvertingCond()
912 if (!MBB->isLayoutSuccessor(BrCond->getOperand(1).getMBB())) in matchOptBrCondByInvertingCond()
920 MachineInstr *BrCond = &*std::prev(BrIt); in applyOptBrCondByInvertingCond() local
922 Builder.setInstrAndDebugLoc(*BrCond); in applyOptBrCondByInvertingCond()
923 LLT Ty = MRI.getType(BrCond->getOperand(0).getReg()); in applyOptBrCondByInvertingCond()
929 auto Xor = Builder.buildXor(Ty, BrCond->getOperand(0), True); in applyOptBrCondByInvertingCond()
931 auto *FallthroughBB = BrCond->getOperand(1).getMBB(); in applyOptBrCondByInvertingCond()
938 Observer.changingInstr(*BrCond); in applyOptBrCondByInvertingCond()
939 BrCond->getOperand(0).setReg(Xor.getReg(0)); in applyOptBrCondByInvertingCond()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.cpp | 2357 if (MachineInstr *BrCond = verifyCFIntrinsic(MI, MRI, Br)) { in legalizeIntrinsic() local
2361 B.setInstr(*BrCond); in legalizeIntrinsic()
2365 MachineBasicBlock *BrTarget = BrCond->getOperand(1).getMBB(); in legalizeIntrinsic()
2383 Br->getOperand(0).setMBB(BrCond->getOperand(1).getMBB()); in legalizeIntrinsic()
2388 BrCond->eraseFromParent(); in legalizeIntrinsic()
2396 if (MachineInstr *BrCond = verifyCFIntrinsic(MI, MRI, Br)) { in legalizeIntrinsic() local
2400 B.setInstr(*BrCond); in legalizeIntrinsic()
2406 .addMBB(BrCond->getOperand(1).getMBB()); in legalizeIntrinsic()
2408 BrCond->eraseFromParent(); in legalizeIntrinsic()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | MachinePipeliner.h | 79 SmallVector<MachineOperand, 4> BrCond; member
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | MachinePipeliner.h | 80 SmallVector<MachineOperand, 4> BrCond; member
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.cpp | 4606 if (MachineInstr *BrCond = in legalizeIntrinsic() local
4614 MachineBasicBlock *CondBrTarget = BrCond->getOperand(1).getMBB(); in legalizeIntrinsic()
4619 B.setInsertPt(B.getMBB(), BrCond->getIterator()); in legalizeIntrinsic()
4644 BrCond->eraseFromParent(); in legalizeIntrinsic()
4654 if (MachineInstr *BrCond = in legalizeIntrinsic() local
4659 MachineBasicBlock *CondBrTarget = BrCond->getOperand(1).getMBB(); in legalizeIntrinsic()
4665 B.setInsertPt(B.getMBB(), BrCond->getIterator()); in legalizeIntrinsic()
4676 BrCond->eraseFromParent(); in legalizeIntrinsic()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 1927 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, in visitSwitchCase() local
1934 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, in visitSwitchCase()
1937 DAG.setRoot(BrCond); in visitSwitchCase()
1991 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, in visitJumpTableHeader() local
1997 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, in visitJumpTableHeader()
2000 DAG.setRoot(BrCond); in visitJumpTableHeader()
2105 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, in visitSPDescriptorParent() local
2110 MVT::Other, BrCond, in visitSPDescriptorParent()
8718 SDValue BrCond = in lowerWorkItem() local
8722 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, in lowerWorkItem()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Utils/ |
| D | SimplifyCFG.cpp | 1966 Value *BrCond = BI->getCondition(); in SpeculativelyExecuteBB() local
1967 if (isa<FCmpInst>(BrCond)) in SpeculativelyExecuteBB()
2106 BrCond, TrueV, FalseV, "spec.store.select", BI); in SpeculativelyExecuteBB()
2140 BrCond, TrueV, FalseV, "spec.select", BI); in SpeculativelyExecuteBB()
2516 Value *BrCond = BI->getCondition(); in SimplifyCondBranchToTwoReturns() local
2524 Builder.CreateSelect(BrCond, TrueValue, FalseValue, "retval", BI); in SimplifyCondBranchToTwoReturns()
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| /external/llvm/lib/Transforms/Utils/ |
| D | SimplifyCFG.cpp | 1598 Value *BrCond = BI->getCondition(); in SpeculativelyExecuteBB() local
1599 if (isa<FCmpInst>(BrCond)) in SpeculativelyExecuteBB()
1735 BrCond, TrueV, FalseV, TrueV->getName() + "." + FalseV->getName(), BI); in SpeculativelyExecuteBB()
1768 BrCond, TrueV, FalseV, TrueV->getName() + "." + FalseV->getName(), BI); in SpeculativelyExecuteBB()
2119 Value *BrCond = BI->getCondition(); in SimplifyCondBranchToTwoReturns() local
2127 Builder.CreateSelect(BrCond, TrueValue, FalseValue, "retval", BI); in SimplifyCondBranchToTwoReturns()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 2420 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, in visitSwitchCase() local
2427 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, in visitSwitchCase()
2430 DAG.setRoot(BrCond); in visitSwitchCase()
2483 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, in visitJumpTableHeader() local
2489 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, in visitJumpTableHeader()
2492 DAG.setRoot(BrCond); in visitJumpTableHeader()
2611 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, in visitSPDescriptorParent() local
2616 MVT::Other, BrCond, in visitSPDescriptorParent()
10155 SDValue BrCond = in lowerWorkItem() local
10159 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, in lowerWorkItem()
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| /external/llvm-project/llvm/lib/Transforms/Utils/ |
| D | SimplifyCFG.cpp | 2116 Value *BrCond = BI->getCondition(); in SpeculativelyExecuteBB() local
2117 if (isa<FCmpInst>(BrCond)) in SpeculativelyExecuteBB()
2229 BrCond, TrueV, FalseV, "spec.store.select", BI); in SpeculativelyExecuteBB()
2267 Value *V = Builder.CreateSelect(BrCond, TrueV, FalseV, "spec.select", BI); in SpeculativelyExecuteBB()
2646 Value *BrCond = BI->getCondition(); in SimplifyCondBranchToTwoReturns() local
2654 Builder.CreateSelect(BrCond, TrueValue, FalseValue, "retval", BI); in SimplifyCondBranchToTwoReturns()
|