Searched refs:Bridge (Results 1 – 25 of 79) sorted by relevance
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| /external/tensorflow/tensorflow/compiler/aot/tests/ |
| D | BUILD | 356 mlir_components = "Bridge",
369 mlir_components = "Bridge",
383 mlir_components = "Bridge",
395 mlir_components = "Bridge",
407 mlir_components = "Bridge",
419 mlir_components = "Bridge",
431 mlir_components = "Bridge",
443 mlir_components = "Bridge",
455 mlir_components = "Bridge",
469 mlir_components = "Bridge",
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| D | test_error_message.lit.pbtxt | 1 # RUN: not tfcompile --graph=%s --config=%s.config.pbtxt --mlir_components=Bridge --debug_info=%s.d…
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| /external/tensorflow/tensorflow/compiler/mlir/tensorflow/g3doc/ |
| D | enable_mlir_bridge.md | 1 # Enable MLIR-Based new TPU Bridge
3 **MLIR-Based new TPU Bridge is an experimental feature, tread lightly.**
8 Bridge is enabled or not. You can set it by using the following example code:
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| /external/tcpdump/tests/ |
| D | lldp_cdp-ev.out | 50 System Capabilities [Bridge, Router] (0x0014)
51 Enabled Capabilities [Bridge] (0x0004)
72 System Capabilities [Bridge, Router] (0x0014)
73 Enabled Capabilities [Bridge] (0x0004)
94 System Capabilities [Bridge, Router] (0x0014)
95 Enabled Capabilities [Bridge] (0x0004)
116 System Capabilities [Bridge, Router] (0x0014)
117 Enabled Capabilities [Bridge] (0x0004)
176 System Capabilities [Bridge, Router] (0x0014)
177 Enabled Capabilities [Bridge] (0x0004)
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| D | lldp_mudurl-v.out | 11 System Capabilities [Bridge, WLAN AP, Router, Station Only] (0x009c)
42 System Capabilities [Bridge, WLAN AP, Router, Station Only] (0x009c)
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| D | lldp-infinite-loop-2.out | 29 EVB Bridge Status
33 R: 7, RTE: 21, EVB Mode: EVB Bridge [1]
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| D | lldp_mudurl-vv.out | 22 System Capabilities [Bridge, WLAN AP, Router, Station Only] (0x009c)
75 System Capabilities [Bridge, WLAN AP, Router, Station Only] (0x009c)
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| D | evb.out | 50 EVB Bridge Status
54 R: 7, RTE: 20, EVB Mode: EVB Bridge [1]
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| /external/tensorflow/tensorflow/compiler/aot/ |
| D | BUILD | 175 mlir_components = "Bridge",
202 mlir_components = "Bridge",
229 mlir_components = "Bridge",
255 mlir_components = "Bridge",
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| /external/ppp/pppd/plugins/radius/etc/ |
| D | dictionary.ascend | 62 ATTRIBUTE Ascend-Bridge-Address 168 string
124 ATTRIBUTE Ascend-Bridge 230 integer
188 VALUE Ascend-Bridge Bridge-No 0
189 VALUE Ascend-Bridge Bridge-Yes 1
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| /external/llvm-project/lldb/bindings/lua/ |
| D | lua.swig | 6 liblldb Script Bridge functions.
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| /external/autotest/server/site_tests/apmanager_SimpleConnect/ |
| D | control.bridge | 19 # Bridge mode configuration.
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| /external/llvm/lib/Target/X86/ |
| D | X86SchedSandyBridge.td | 1 //=- X86SchedSandyBridge.td - X86 Sandy Bridge Scheduling ----*- tablegen -*-=//
10 // This file defines the machine model for Sandy Bridge to support instruction
34 // Sandy Bridge can issue micro-ops to 6 different ports in one cycle.
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| /external/llvm-project/lldb/test/Shell/ScriptInterpreter/Python/Crashlog/Inputs/ |
| D | a.out.crash | 12 Bridge OS Version: redacted
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| /external/igt-gpu-tools/man/ |
| D | intel_panel_fitter.rst | 34 Pipe to be used (A, B or C, but C is only present on Ivy Bridge and newer).
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| /external/mesa3d/docs/relnotes/ |
| D | 11.0.8.rst | 77 - Revert "i965/vec4: Use byte offsets for UBO pulls on Sandy Bridge"
112 - i965/vec4: Use byte offsets for UBO pulls on Sandy Bridge
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| /external/cpu_features/ |
| D | README.md | 100 the most efficient (e.g. AVX on Sandy Bridge). We provide a function to retrieve
104 set—but only if it's not Sandy Bridge.
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| /external/tensorflow/tensorflow/compiler/mlir/tosa/ |
| D | BUILD | 1 # TensorFlow -> TOSA Compiler Bridge.
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| /external/angle/ |
| D | CONTRIBUTORS | 27 Henry Bridge
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86SchedSandyBridge.td | 1 //=- X86SchedSandyBridge.td - X86 Sandy Bridge Scheduling ----*- tablegen -*-=//
9 // This file defines the machine model for Sandy Bridge to support instruction
37 // Sandy Bridge can issue micro-ops to 6 different ports in one cycle.
191 // NOTE: These don't exist on Sandy Bridge. Ports are guesses.
1114 // section "Sandy Bridge and Ivy Bridge Pipeline" > "Register allocation and
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| D | X86.td | 370 // Sandy Bridge and newer processors can use SHLD with the same source on both
378 // Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka
400 // Sandy Bridge and newer processors have many instructions that can be
1388 // We currently use the Sandy Bridge model as the default scheduling model as
1389 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86SchedSandyBridge.td | 1 //=- X86SchedSandyBridge.td - X86 Sandy Bridge Scheduling ----*- tablegen -*-=//
9 // This file defines the machine model for Sandy Bridge to support instruction
37 // Sandy Bridge can issue micro-ops to 6 different ports in one cycle.
191 // NOTE: These don't exist on Sandy Bridge. Ports are guesses.
1111 // section "Sandy Bridge and Ivy Bridge Pipeline" > "Register allocation and
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| D | X86.td | 342 // Sandy Bridge and newer processors can use SHLD with the same source on both
350 // Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka
366 // Sandy Bridge and newer processors have many instructions that can be
1228 // We currently use the Sandy Bridge model as the default scheduling model as
1229 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
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| /external/mesa3d/docs/ |
| D | index.rst | 155 Intel Sandy Bridge and Ivy Bridge is the only driver to support OpenGL
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| /external/openssh/ |
| D | README.tun | 98 --- real connection Bridge -> | +----------+
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