| /external/crosvm/devices/src/ |
| D | direct_io.rs | 5 use crate::{BusAccessInfo, BusDevice, BusDeviceSync};
48 fn read(&mut self, ai: BusAccessInfo, data: &mut [u8]) { in read() argument
53 fn write(&mut self, ai: BusAccessInfo, data: &[u8]) { in write() argument
60 fn read(&self, ai: BusAccessInfo, data: &mut [u8]) { in read() argument
65 fn write(&self, ai: BusAccessInfo, data: &[u8]) { in write() argument
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| D | pl030.rs | 9 use crate::{BusAccessInfo, BusDevice};
78 fn write(&mut self, info: BusAccessInfo, data: &[u8]) { in write() argument
121 fn read(&mut self, info: BusAccessInfo, data: &mut [u8]) { in read() argument
154 fn pl030_bus_address(offset: u64) -> BusAccessInfo { in pl030_bus_address() argument
155 BusAccessInfo { in pl030_bus_address()
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| D | i8042.rs | 7 use crate::{BusAccessInfo, BusDevice};
28 fn read(&mut self, info: BusAccessInfo, data: &mut [u8]) { in read() argument
38 fn write(&mut self, info: BusAccessInfo, data: &[u8]) { in write() argument
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| D | proxy.rs | 17 use crate::{BusAccessInfo, BusDevice};
44 info: BusAccessInfo,
48 info: BusAccessInfo,
266 fn read(&mut self, info: BusAccessInfo, data: &mut [u8]) { in read() argument
276 fn write(&mut self, info: BusAccessInfo, data: &[u8]) { in write() argument
315 fn write(&mut self, _info: BusAccessInfo, data: &[u8]) { in write() argument
320 fn read(&mut self, _info: BusAccessInfo, data: &mut [u8]) { in read() argument
363 let address = BusAccessInfo { in test_proxied_read_write()
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| D | bus.rs | 18 pub struct BusAccessInfo { struct
28 impl std::fmt::Display for BusAccessInfo { argument
62 fn read(&mut self, offset: BusAccessInfo, data: &mut [u8]) {} in read() argument
64 fn write(&mut self, offset: BusAccessInfo, data: &[u8]) {} in write() argument
88 fn read(&self, offset: BusAccessInfo, data: &mut [u8]); in read() argument
89 fn write(&self, offset: BusAccessInfo, data: &[u8]); in write() argument
276 let io = BusAccessInfo { in read()
296 let io = BusAccessInfo { in write()
345 fn read(&mut self, info: BusAccessInfo, data: &mut [u8]) { in read() argument
356 fn write(&mut self, info: BusAccessInfo, data: &[u8]) { in write() argument
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| D | cmos.rs | 9 use crate::{BusAccessInfo, BusDevice};
54 fn write(&mut self, info: BusAccessInfo, data: &[u8]) { in write() argument
66 fn read(&mut self, info: BusAccessInfo, data: &mut [u8]) { in read() argument
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| D | acpi.rs | 5 use crate::{BusAccessInfo, BusDevice, BusResumeDevice};
59 fn read(&mut self, info: BusAccessInfo, data: &mut [u8]) { in read() argument
80 fn write(&mut self, info: BusAccessInfo, data: &[u8]) { in write() argument
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| D | serial.rs | 14 use crate::bus::BusAccessInfo;
314 fn write(&mut self, info: BusAccessInfo, data: &[u8]) { in write() argument
324 fn read(&mut self, info: BusAccessInfo, data: &mut [u8]) { in read() argument
407 fn serial_bus_address(offset: u8) -> BusAccessInfo { in serial_bus_address() argument
409 BusAccessInfo { in serial_bus_address()
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| D | pit.rs | 30 use crate::bus::BusAccessInfo;
218 fn write(&mut self, info: BusAccessInfo, data: &[u8]) { in write() argument
235 fn read(&mut self, info: BusAccessInfo, data: &mut [u8]) { in read() argument
930 fn pit_bus_address(address: PortIOSpace) -> BusAccessInfo { in pit_bus_address() argument
944 BusAccessInfo { in pit_bus_address()
1453 BusAccessInfo { in invalid_write_and_read()
1461 BusAccessInfo { in invalid_write_and_read()
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| D | bat.rs | 5 use crate::{BusAccessInfo, BusDevice};
430 fn read(&mut self, info: BusAccessInfo, data: &mut [u8]) { in read() argument
470 fn write(&mut self, info: BusAccessInfo, data: &[u8]) { in write() argument
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| D | lib.rs | 34 pub use self::bus::{Bus, BusAccessInfo, BusDevice, BusDeviceSync, BusRange, BusResumeDevice};
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| /external/crosvm/devices/src/pci/ |
| D | pci_root.rs | 17 use crate::{BusAccessInfo, BusDevice};
254 fn read(&mut self, info: BusAccessInfo, data: &mut [u8]) { in read() argument
276 fn write(&mut self, info: BusAccessInfo, data: &[u8]) { in write() argument
314 fn read(&mut self, info: BusAccessInfo, data: &mut [u8]) { in read() argument
331 fn write(&mut self, info: BusAccessInfo, data: &[u8]) { in write() argument
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| D | pci_device.rs | 18 use crate::{BusAccessInfo, BusDevice};
138 fn read(&mut self, info: BusAccessInfo, data: &mut [u8]) { in read() argument
142 fn write(&mut self, info: BusAccessInfo, data: &[u8]) { in write() argument
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| /external/crosvm/devices/src/irqchip/ |
| D | ioapic.rs | 12 use crate::bus::BusAccessInfo;
93 fn read(&mut self, info: BusAccessInfo, data: &mut [u8]) { in read() argument
119 fn write(&mut self, info: BusAccessInfo, data: &[u8]) { in write() argument
490 fn ioapic_bus_address(offset: u8) -> BusAccessInfo { in ioapic_bus_address() argument
492 BusAccessInfo { in ioapic_bus_address()
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| D | pic.rs | 15 use crate::bus::BusAccessInfo;
91 fn write(&mut self, info: BusAccessInfo, data: &[u8]) { in write() argument
107 fn read(&mut self, info: BusAccessInfo, data: &mut [u8]) { in read() argument
543 fn pic_bus_address(address: u64) -> BusAccessInfo { in pic_bus_address() argument
554 BusAccessInfo { in pic_bus_address()
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