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Searched refs:CDRU_GENPLL2_CONTROL1 (Results 1 – 2 of 2) sorted by relevance

/external/arm-trusted-firmware/plat/brcm/board/stingray/include/
Dcrmu_def.h129 #define CDRU_GENPLL2_CONTROL1 (CDRU_BASE_ADDR + 0x1b0) macro
/external/arm-trusted-firmware/plat/brcm/board/stingray/src/
Dfsx.c472 mmio_setbits_32(CDRU_GENPLL2_CONTROL1, in fs4_disable_clocks()