| /external/llvm-project/llvm/utils/TableGen/ |
| D | InfoByHwMode.cpp | 32 ValueTypeByHwMode::ValueTypeByHwMode(Record *R, const CodeGenHwModes &CGH) { in ValueTypeByHwMode() argument
33 const HwModeSelect &MS = CGH.getHwModeSelect(R); in ValueTypeByHwMode()
110 const CodeGenHwModes &CGH) { in getValueTypeByHwMode() argument
118 return ValueTypeByHwMode(Rec, CGH); in getValueTypeByHwMode()
122 RegSizeInfo::RegSizeInfo(Record *R, const CodeGenHwModes &CGH) { in RegSizeInfo() argument
145 const CodeGenHwModes &CGH) { in RegSizeInfoByHwMode() argument
146 const HwModeSelect &MS = CGH.getHwModeSelect(R); in RegSizeInfoByHwMode()
148 auto I = Map.insert({P.first, RegSizeInfo(P.second, CGH)}); in RegSizeInfoByHwMode()
195 EncodingInfoByHwMode::EncodingInfoByHwMode(Record *R, const CodeGenHwModes &CGH) { in EncodingInfoByHwMode() argument
196 const HwModeSelect &MS = CGH.getHwModeSelect(R); in EncodingInfoByHwMode()
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| D | InfoByHwMode.h | 121 ValueTypeByHwMode(Record *R, const CodeGenHwModes &CGH);
146 const CodeGenHwModes &CGH);
153 RegSizeInfo(Record *R, const CodeGenHwModes &CGH);
169 RegSizeInfoByHwMode(Record *R, const CodeGenHwModes &CGH);
188 EncodingInfoByHwMode(Record *R, const CodeGenHwModes &CGH);
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| D | CodeGenHwModes.cpp | 31 HwModeSelect::HwModeSelect(Record *R, CodeGenHwModes &CGH) { in HwModeSelect() argument
41 unsigned ModeId = CGH.getHwModeId(Modes[i]->getName()); in HwModeSelect()
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| D | CodeGenTarget.h | 56 CodeGenHwModes CGH; variable
141 const CodeGenHwModes &getHwModes() const { return CGH; } in getHwModes()
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| D | CodeGenHwModes.h | 36 HwModeSelect(Record *R, CodeGenHwModes &CGH);
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| D | RegisterInfoEmitter.cpp | 1240 const CodeGenHwModes &CGH = Target.getHwModes(); in runTargetDesc() local
1241 unsigned NumModes = CGH.getNumModeIds(); in runTargetDesc()
1288 OS << CGH.getMode(M).Name; in runTargetDesc()
1637 const CodeGenHwModes &CGH = Target.getHwModes(); in debugDump() local
1638 unsigned NumModes = CGH.getNumModeIds(); in debugDump()
1639 auto getModeName = [CGH] (unsigned M) -> StringRef { in debugDump()
1642 return CGH.getMode(M).Name; in debugDump()
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| D | CodeGenRegisters.h | 533 const CodeGenHwModes &CGH; variable
626 const CodeGenHwModes &getHwModes() const { return CGH; } in getHwModes()
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| D | CodeGenDAGPatterns.cpp | 1450 SDTypeConstraint::SDTypeConstraint(Record *R, const CodeGenHwModes &CGH) { in SDTypeConstraint() argument
1455 VVT = getValueTypeByHwMode(R->getValueAsDef("VT"), CGH); in SDTypeConstraint()
1487 VVT = getValueTypeByHwMode(R->getValueAsDef("VT"), CGH); in SDTypeConstraint()
1727 SDNodeInfo::SDNodeInfo(Record *R, const CodeGenHwModes &CGH) : Def(R) { in SDNodeInfo() argument
1741 TypeConstraints.emplace_back(R, CGH); in SDNodeInfo()
2195 const CodeGenHwModes &CGH = CDP.getTargetInfo().getHwModes(); in getImplicitType() local
2196 return TypeSetByHwMode(getValueTypeByHwMode(R, CGH)); in getImplicitType()
2226 const CodeGenHwModes &CGH = CDP.getTargetInfo().getHwModes(); in getImplicitType() local
2228 return TypeSetByHwMode(getValueTypeByHwMode(T, CGH)); in getImplicitType()
2806 const CodeGenHwModes &CGH = getDAGPatterns().getTargetInfo().getHwModes(); in ParseTreePattern() local
[all …]
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| D | SubtargetEmitter.cpp | 1682 const CodeGenHwModes &CGH = TGT.getHwModes(); in EmitHwModeCheck() local
1683 assert(CGH.getNumModeIds() > 0); in EmitHwModeCheck()
1684 if (CGH.getNumModeIds() == 1) in EmitHwModeCheck()
1688 for (unsigned M = 1, NumModes = CGH.getNumModeIds(); M != NumModes; ++M) { in EmitHwModeCheck()
1689 const HwMode &HM = CGH.getMode(M); in EmitHwModeCheck()
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| D | CodeGenDAGPatterns.h | 377 SDTypeConstraint(Record *R, const CodeGenHwModes &CGH);
456 SDNodeInfo(Record *R, const CodeGenHwModes &CGH);
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| D | CodeGenTarget.cpp | 251 : Records(records), CGH(records) { in CodeGenTarget()
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| D | CodeGenRegisters.cpp | 1109 const CodeGenHwModes &Modes) : CGH(Modes) { in CodeGenRegBank()
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| /external/llvm-project/llvm/test/CodeGen/SystemZ/ |
| D | int-cmp-04.ll | 6 ; Check CGH with no displacement.
19 ; Check the high end of the aligned CGH range.
49 ; Check the high end of the negative aligned CGH range.
63 ; Check the low end of the CGH range.
93 ; Check that CGH allows an index.
109 ; Check the comparison can be reversed if that allows CGH to be used.
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| /external/llvm/test/CodeGen/SystemZ/ |
| D | int-cmp-04.ll | 6 ; Check CGH with no displacement.
19 ; Check the high end of the aligned CGH range.
49 ; Check the high end of the negative aligned CGH range.
63 ; Check the low end of the CGH range.
93 ; Check that CGH allows an index.
109 ; Check the comparison can be reversed if that allows CGH to be used.
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZScheduleZEC12.td | 526 def : InstRW<[WLat2LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "CGH$")>;
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| D | SystemZScheduleZ196.td | 516 def : InstRW<[WLat2LSU, RegReadAdv, FXU2, LSU, GroupAlone], (instregex "CGH$")>;
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| D | SystemZScheduleZ13.td | 554 def : InstRW<[WLat2LSU, RegReadAdv, FXb, LSU, NormalGr], (instregex "CGH$")>;
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| D | SystemZScheduleZ14.td | 564 def : InstRW<[WLat2LSU, RegReadAdv, FXb, LSU, NormalGr], (instregex "CGH$")>;
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| D | SystemZScheduleZ15.td | 578 def : InstRW<[WLat2LSU, RegReadAdv, FXb, LSU, NormalGr], (instregex "CGH$")>;
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| /external/llvm-project/llvm/lib/Target/SystemZ/ |
| D | SystemZScheduleZ196.td | 516 def : InstRW<[WLat2LSU, RegReadAdv, FXU2, LSU, GroupAlone], (instregex "CGH$")>;
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| D | SystemZScheduleZEC12.td | 526 def : InstRW<[WLat2LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "CGH$")>;
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| D | SystemZScheduleZ13.td | 554 def : InstRW<[WLat2LSU, RegReadAdv, FXb, LSU, NormalGr], (instregex "CGH$")>;
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| D | SystemZScheduleZ14.td | 564 def : InstRW<[WLat2LSU, RegReadAdv, FXb, LSU, NormalGr], (instregex "CGH$")>;
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| /external/capstone/arch/SystemZ/ |
| D | SystemZGenAsmWriter.inc | 2816 134240617U, // CGH
5619 0U, // CGH
8422 0U, // CGH
10887 // BAL, BAS, C, CD, CDB, CE, CEB, CG, CGF, CGH, CH, CHF, CHY, CL, CLG, CL...
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.td | 1301 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>;
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