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Searched refs:CIK_UCONFIG_REG_END (Results 1 – 6 of 6) sorted by relevance

/external/mesa3d/src/amd/vulkan/
Dradv_cs.h132 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_seq()
142 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_seq_perfctr()
160 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_idx()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_cs.h186 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_seq()
202 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_idx()
Dr600d_common.h34 #define CIK_UCONFIG_REG_END 0x00038000 macro
/external/mesa3d/src/amd/common/
Dsid.h37 #define CIK_UCONFIG_REG_END 0x00040000 macro
44 #define SI_UCONFIG_REG_SPACE_SIZE (CIK_UCONFIG_REG_END - CIK_UCONFIG_REG_OFFSET)
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_build_pm4.h108 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_seq()
124 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_idx()
Dsi_pm4.c69 } else if (reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END) { in si_pm4_set_reg()