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Searched refs:CIK_UCONFIG_REG_OFFSET (Results 1 – 8 of 8) sorted by relevance

/external/mesa3d/src/amd/vulkan/
Dradv_cs.h132 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_seq()
136 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2); in radeon_set_uconfig_reg_seq()
142 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_seq_perfctr()
146 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2); in radeon_set_uconfig_reg_seq_perfctr()
160 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_idx()
170 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28)); in radeon_set_uconfig_reg_idx()
178 assert(reg < CIK_UCONFIG_REG_OFFSET); in radeon_set_privileged_config_reg()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_cs.h186 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_seq()
189 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2); in radeon_set_uconfig_reg_seq()
202 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_idx()
205 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28)); in radeon_set_uconfig_reg_idx()
Dr600d_common.h33 #define CIK_UCONFIG_REG_OFFSET 0x00030000 macro
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_build_pm4.h108 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_seq()
111 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2); in radeon_set_uconfig_reg_seq()
124 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_idx()
132 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28)); in radeon_set_uconfig_reg_idx()
Dsi_pm4.c69 } else if (reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END) { in si_pm4_set_reg()
71 reg -= CIK_UCONFIG_REG_OFFSET; in si_pm4_set_reg()
Dsi_cp_reg_shadowing.c44 offset = CIK_UCONFIG_REG_OFFSET; in si_build_load_reg()
/external/mesa3d/src/amd/common/
Dsid.h36 #define CIK_UCONFIG_REG_OFFSET 0x00030000 macro
44 #define SI_UCONFIG_REG_SPACE_SIZE (CIK_UCONFIG_REG_END - CIK_UCONFIG_REG_OFFSET)
Dac_debug.c273 ac_parse_set_reg_packet(f, count, CIK_UCONFIG_REG_OFFSET, ib); in ac_parse_packet3()