| /external/arm-trusted-firmware/fdts/ |
| D | fvp-defs.dtsi | 34 #define CLS(n) (n / CPUS_PER_CLUSTER) macro
87 #if (CLS(1) == 0)
99 #if (CLS(2) == 0)
102 #elif (CLS(2) == 1)
114 #if (CLS(3) == 0)
116 #elif (CLS(3) == 1)
134 #if (CLS(4) == 1)
146 #if (CLS(5) == 1)
163 #if (CLS(6) == 1)
166 #elif (CLS(6) == 2)
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/ |
| D | LoopCacheAnalysis.cpp | 142 unsigned CLS, in hasSpacialReuse() argument
184 bool InSameCacheLine = (Diff->getValue()->getSExtValue() < CLS); in hasSpacialReuse()
256 unsigned CLS) const { in computeRefCost()
282 if (isConsecutive(L, CLS)) { in computeRefCost()
286 const SCEV *CacheLineSize = SE.getConstant(Stride->getType(), CLS); in computeRefCost()
382 bool IndexedReference::isConsecutive(const Loop &L, unsigned CLS) const { in isConsecutive()
397 const SCEV *CacheLineSize = SE.getConstant(Stride->getType(), CLS); in isConsecutive()
518 unsigned CLS = TTI.getCacheLineSize(); in populateReferenceGroups() local
543 R->hasSpacialReuse(Representative, CLS, AA); in populateReferenceGroups()
|
| /external/llvm-project/llvm/lib/Analysis/ |
| D | LoopCacheAnalysis.cpp | 151 unsigned CLS, in hasSpacialReuse() argument
193 bool InSameCacheLine = (Diff->getValue()->getSExtValue() < CLS); in hasSpacialReuse()
265 unsigned CLS) const { in computeRefCost()
291 if (isConsecutive(L, CLS)) { in computeRefCost()
295 const SCEV *CacheLineSize = SE.getConstant(Stride->getType(), CLS); in computeRefCost()
407 bool IndexedReference::isConsecutive(const Loop &L, unsigned CLS) const { in isConsecutive()
422 const SCEV *CacheLineSize = SE.getConstant(Stride->getType(), CLS); in isConsecutive()
544 unsigned CLS = TTI.getCacheLineSize(); in populateReferenceGroups() local
581 R->hasSpacialReuse(Representative, CLS, AA); in populateReferenceGroups()
|
| /external/mdnsresponder/mDNSWindows/DNSServiceBrowser/WindowsCE/ |
| D | Application.vcc | 18 [CLS:Application]
24 [CLS:BrowserDialog]
|
| /external/llvm-project/llvm/include/llvm/Analysis/ |
| D | LoopCacheAnalysis.h | 73 Optional<bool> hasSpacialReuse(const IndexedReference &Other, unsigned CLS,
93 CacheCostTy computeRefCost(const Loop &L, unsigned CLS) const;
106 bool isConsecutive(const Loop &L, unsigned CLS) const;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Analysis/ |
| D | LoopCacheAnalysis.h | 72 Optional<bool> hasSpacialReuse(const IndexedReference &Other, unsigned CLS,
92 CacheCostTy computeRefCost(const Loop &L, unsigned CLS) const;
105 bool isConsecutive(const Loop &L, unsigned CLS) const;
|
| /external/llvm-project/clang/test/CodeGenObjC/ |
| D | gnu-init.m | 77 …K-WIN-DAG: @"__start_.objcrt$CLS" = linkonce_odr hidden global %.objc_section_sentinel zeroinitial…
78 …ECK-WIN-DAG: @"__stop.objcrt$CLS" = linkonce_odr hidden global %.objc_section_sentinel zeroinitial…
91 …t$SEL", %.objc_section_sentinel* @"__start_.objcrt$CLS", %.objc_section_sentinel* @"__stop.objcrt$…
|
| /external/icu/icu4j/tools/build/src/com/ibm/icu/dev/tool/docs/ |
| D | APIInfo.java | 40 public static final int CLS = 8; field in APIInfo
111 public void setClassName(String val) { setType(CLS, val); } in setClassName()
137 public String getClassName() { return get(CLS, true); } in getClassName()
171 case CLS: return cls; in get()
209 case CLS: cls = val; break; in setType()
|
| D | CheckAPI.java | 92 private static final int CLS = 8; field in CheckAPI
123 case CLS: return cls; in get()
145 case CLS: cls = val; break; in setType()
332 …setType(CLS, (doc.isClass() || doc.isInterface() || (doc.containingClass() == null)) ? "" : doc.co… in read()
868 String name = info.get(CLS, true); in writeResults()
947 String cls = info.get(CLS, true); in stripClassInfo()
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZPatterns.td | 20 // in which the first operand has class CLS and which the second operand
57 // Record that INSN performs insertion TYPE into a register of class CLS.
149 // registers in CLS against zero. The instruction has separate R1 and R2
158 // on registers of class CLS.
|
| /external/llvm-project/llvm/lib/Target/SystemZ/ |
| D | SystemZPatterns.td | 19 // in which the first operand has class CLS and which the second operand
56 // Record that INSN performs insertion TYPE into a register of class CLS.
148 // registers in CLS against zero. The instruction has separate R1 and R2
157 // on registers of class CLS.
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZPatterns.td | 19 // in which the first operand has class CLS and which the second operand
56 // Record that INSN performs insertion TYPE into a register of class CLS.
148 // registers in CLS against zero. The instruction has separate R1 and R2
157 // on registers of class CLS.
|
| /external/llvm-project/llvm/test/MC/AVR/ |
| D | inst-family-set-clr-flag.s | 58 ; CLS
|
| /external/libcups/backend/ |
| D | snmp.txt | 61 …s.11.2.3.9.1.1.7.0 = STRING: "MFG:EPSON;CMD:ESCPL2,BDC;MDL:Stylus Pro 7600;CLS:PRINTER;DES:EPSON S…
62 …48.1.2.2.1.1.1.1.1 = STRING: "MFG:EPSON;CMD:ESCPL2,BDC;MDL:Stylus Pro 7600;CLS:PRINTER;DES:EPSON S…
|
| /external/protobuf/csharp/ |
| D | CHANGES.txt | 113 non-CLS-compliance.
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | sve-intrinsics-counting-bits.ll | 8 ; CLS
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 150 // CLS,CLZ,RBIT,REV,REV16,REV32
500 // CLS,CLZ,CNT,RBIT,REV16,REV32,REV64,XTN
|
| D | AArch64SchedTSV110.td | 406 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(CLS|CLZ|RBIT|REV(16|32)?)(W|X)r$")>;
644 def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(CLS|CLZ|CNT)v")>;
|
| D | AArch64SchedFalkorDetails.td | 922 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(CLS|CLZ|CNT|RBIT)(v2i32|v4i16|v8i8)$")>;
944 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(CLS|CLZ|CNT|RBIT)(v4i32|v8i16|v16i8)$")>;
1207 def : InstRW<[FalkorWr_1XYZ_2cyc], (instregex "^(CLS|CLZ|RBIT|REV|REV16|REV32)(W|X)r$")>;
|
| D | AArch64SchedKryoDetails.td | 495 (instregex "(CLS|CLZ)(W|X)r")>;
501 (instregex "(CLS|CLZ|CNT)(v4i32|v8i16|v16i8)")>;
507 (instregex "(CLS|CLZ|CNT)(v2i32|v4i16|v8i8)")>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 149 // CLS,CLZ,RBIT,REV,REV16,REV32
499 // CLS,CLZ,CNT,RBIT,REV16,REV32,REV64,XTN
|
| D | AArch64SchedFalkorDetails.td | 922 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(CLS|CLZ|CNT|RBIT)(v2i32|v4i16|v8i8)$")>;
944 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(CLS|CLZ|CNT|RBIT)(v4i32|v8i16|v16i8)$")>;
1207 def : InstRW<[FalkorWr_1XYZ_2cyc], (instregex "^(CLS|CLZ|RBIT|REV|REV16|REV32)(W|X)r$")>;
|
| D | AArch64SchedKryoDetails.td | 495 (instregex "(CLS|CLZ)(W|X)r")>;
501 (instregex "(CLS|CLZ|CNT)(v4i32|v8i16|v16i8)")>;
507 (instregex "(CLS|CLZ|CNT)(v2i32|v4i16|v8i8)")>;
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 148 // CLS,CLZ,RBIT,REV,REV16,REV32
498 // CLS,CLZ,CNT,RBIT,REV16,REV32,REV64,XTN
|
| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 1423 CLS = DataProcessing1SourceFixed | 0x00001400, enumerator
1424 CLS_w = CLS,
1425 CLS_x = CLS | SixtyFourBits,
|