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Searched refs:COND (Results 1 – 25 of 371) sorted by relevance

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/external/mesa3d/src/gallium/drivers/etnaviv/
Detnaviv_asm.c75 COND(inst->sat, VIV_ISA_WORD_0_SAT) | in etna_assemble()
76 COND(inst->dst.use, VIV_ISA_WORD_0_DST_USE) | in etna_assemble()
83 COND(inst->src[0].use, VIV_ISA_WORD_1_SRC0_USE) | in etna_assemble()
85 COND(inst->type & 0x4, VIV_ISA_WORD_1_TYPE_BIT2) | in etna_assemble()
87 COND(inst->src[0].neg, VIV_ISA_WORD_1_SRC0_NEG) | in etna_assemble()
88 COND(inst->src[0].abs, VIV_ISA_WORD_1_SRC0_ABS); in etna_assemble()
91 COND(inst->src[1].use, VIV_ISA_WORD_2_SRC1_USE) | in etna_assemble()
93 COND(inst->opcode & 0x40, VIV_ISA_WORD_2_OPCODE_BIT6) | in etna_assemble()
95 COND(inst->src[1].neg, VIV_ISA_WORD_2_SRC1_NEG) | in etna_assemble()
96 COND(inst->src[1].abs, VIV_ISA_WORD_2_SRC1_ABS) | in etna_assemble()
[all …]
Detnaviv_rasterizer.c53 COND(so->point_quad_rasterization, VIVS_PA_CONFIG_POINT_SPRITE_ENABLE) | in etna_rasterizer_state_create()
54 COND(so->point_size_per_vertex, VIVS_PA_CONFIG_POINT_SIZE_ENABLE) | in etna_rasterizer_state_create()
55 … COND(VIV_FEATURE(ctx->screen, chipMinorFeatures1, WIDE_LINE), VIVS_PA_CONFIG_WIDE_LINE); in etna_rasterizer_state_create()
60 cs->SE_CONFIG = COND(so->line_last_pixel, VIVS_SE_CONFIG_LAST_PIXEL_ENABLE); in etna_rasterizer_state_create()
64 COND(!so->flatshade_first, VIVS_PA_SYSTEM_MODE_PROVOKING_VERTEX_LAST) | in etna_rasterizer_state_create()
65 COND(so->half_pixel_center, VIVS_PA_SYSTEM_MODE_HALF_PIXEL_CENTER); in etna_rasterizer_state_create()
/external/llvm-project/llvm/test/Transforms/Util/
Dlibcalls-shrinkwrap-double.ll13 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
14 ; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]]…
23 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
24 ; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]]…
33 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
34 ; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]]…
43 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
44 ; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]]…
51 ; CHECK: [[COND:%[0-9]+]] = fcmp ogt double %value, 7.090000e+02
52 ; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]]…
[all …]
Dlibcalls-shrinkwrap-float.ll13 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
14 ; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]]…
23 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
24 ; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]]…
33 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
34 ; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]]…
43 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
44 ; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]]…
51 ; CHECK: [[COND:%[0-9]+]] = fcmp ogt float %value, 8.800000e+01
52 ; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]]…
[all …]
Dlibcalls-shrinkwrap-long-double.ll13 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
14 ; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]]…
23 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
24 ; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]]…
33 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
34 ; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]]…
43 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
44 ; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]]…
51 ; CHECK: [[COND:%[0-9]+]] = fcmp ogt x86_fp80 %value, 0xK400CB170000000000000
52 ; CHECK: br i1 [[COND]], label %[[CALL_LABEL:cdce.call[0-9]*]], label %[[END_LABEL:cdce.end[0-9]*]]…
[all …]
/external/skqp/include/gpu/
DGrConfig.h144 #define GR_ALWAYSASSERT(COND) \ argument
146 if (!(COND)) { \
147 SkDebugf("%s %s failed\n", GR_FILE_AND_LINE_STR, #COND); \
158 #define GR_DEBUGASSERT(COND) GR_ALWAYSASSERT(COND) argument
160 #define GR_DEBUGASSERT(COND) argument
167 #define GrAlwaysAssert(COND) GR_ALWAYSASSERT(COND) argument
/external/libopus/silk/
Dtypedef.h57 # define silk_assert(COND) _ASSERTE(COND) argument
75 # define silk_assert(COND) {if (!(COND)) {silk_fatal("assertion failed: " #COND);}} argument
77 # define silk_assert(COND) argument
/external/llvm-project/llvm/test/Analysis/ValueTracking/
Dnumsignbits-from-assume.ll7 ; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[ADD]], 43
8 ; CHECK-NEXT: call void @llvm.assume(i1 [[COND]])
22 ; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[ADD]], 43
23 ; CHECK-NEXT: call void @llvm.assume(i1 [[COND]])
37 ; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[SUB]], 43
38 ; CHECK-NEXT: call void @llvm.assume(i1 [[COND]])
52 ; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[SUB]], 43
53 ; CHECK-NEXT: call void @llvm.assume(i1 [[COND]])
67 ; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[SUB]], 43
68 ; CHECK-NEXT: call void @llvm.assume(i1 [[COND]])
[all …]
/external/llvm-project/llvm/test/Transforms/SimplifyCFG/X86/
Dspeculate-cttz-ctlz.ll12 ; BMI-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i64 64, i64 [[TMP0]]
13 ; BMI-NEXT: ret i64 [[COND]]
26 ; GENERIC-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i64 64, i64 [[TMP0]]
27 ; GENERIC-NEXT: ret i64 [[COND]]
47 ; BMI-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 32, i32 [[TMP0]]
48 ; BMI-NEXT: ret i32 [[COND]]
61 ; GENERIC-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 32, i32 [[TMP0]]
62 ; GENERIC-NEXT: ret i32 [[COND]]
83 ; BMI-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i16 16, i16 [[TMP0]]
84 ; BMI-NEXT: ret i16 [[COND]]
[all …]
/external/llvm-project/llvm/test/Transforms/AggressiveInstCombine/
Dtrunc_select_cmp.ll10 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 109, i32 [[CONV]]
11 ; CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[COND]] to i16
28 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[CONV2]], i32 [[CONV]]
29 ; CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[COND]] to i16
47 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[CONV2]], i32 [[CONV]]
48 ; CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[COND]] to i16
66 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[CONV2]], i32 [[CONV]]
67 ; CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[COND]] to i16
85 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[CONV2]], i32 [[CONV]]
86 ; CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[COND]] to i16
[all …]
/external/mesa3d/src/gallium/drivers/freedreno/a5xx/
Dfd5_program.c181 COND(ncomp[0] > 0, A5XX_VPC_SO_BUF_CNTL_BUF0) | in emit_stream_out()
182 COND(ncomp[1] > 0, A5XX_VPC_SO_BUF_CNTL_BUF1) | in emit_stream_out()
183 COND(ncomp[2] > 0, A5XX_VPC_SO_BUF_CNTL_BUF2) | in emit_stream_out()
184 COND(ncomp[3] > 0, A5XX_VPC_SO_BUF_CNTL_BUF3)); in emit_stream_out()
334 COND(s[VS].v, A5XX_HLSQ_VS_CONFIG_ENABLED)); in fd5_program_emit()
337 COND(s[FS].v, A5XX_HLSQ_FS_CONFIG_ENABLED)); in fd5_program_emit()
340 COND(s[HS].v, A5XX_HLSQ_HS_CONFIG_ENABLED)); in fd5_program_emit()
343 COND(s[DS].v, A5XX_HLSQ_DS_CONFIG_ENABLED)); in fd5_program_emit()
346 COND(s[GS].v, A5XX_HLSQ_GS_CONFIG_ENABLED)); in fd5_program_emit()
353 COND(s[VS].v && s[VS].v->has_ssbo, A5XX_HLSQ_VS_CNTL_SSBO_ENABLE)); in fd5_program_emit()
[all …]
Dfd5_emit.h127 OUT_RING(ring, COND(mode == GMEM, CP_SET_RENDER_MODE_3_GMEM_ENABLE) | in fd5_set_render_mode()
128 COND(mode == BINNING, CP_SET_RENDER_MODE_3_VSC_ENABLE)); in fd5_set_render_mode()
164 COND(binning, A5XX_RB_RENDER_CNTL_BINNING_PASS) | in fd5_emit_render_cntl()
165 COND(binning, A5XX_RB_RENDER_CNTL_DISABLE_COLOR_PIPE) | in fd5_emit_render_cntl()
166 COND(samples_passed, A5XX_RB_RENDER_CNTL_SAMPLES_PASSED) | in fd5_emit_render_cntl()
167 COND(!blit, 0x8)); in fd5_emit_render_cntl()
171 COND(binning, A5XX_GRAS_SC_CNTL_BINNING_PASS) | in fd5_emit_render_cntl()
172 COND(samples_passed, A5XX_GRAS_SC_CNTL_SAMPLES_PASSED)); in fd5_emit_render_cntl()
Dfd5_blend.c97 COND(cso->logicop_enable, A5XX_RB_MRT_CONTROL_ROP_ENABLE) | in fd5_blend_state_create()
119 COND(cso->alpha_to_coverage, A5XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE) | in fd5_blend_state_create()
120 COND(cso->independent_blend_enable, A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND); in fd5_blend_state_create()
122 COND(cso->alpha_to_coverage, A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE) | in fd5_blend_state_create()
123 COND(mrt_blend, A5XX_SP_BLEND_CNTL_ENABLED); in fd5_blend_state_create()
/external/llvm-project/llvm/test/Transforms/InstSimplify/
Dfcmp-select.ll56 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], double [[X]], double 0.000000e+00
57 ; CHECK-NEXT: ret double [[COND]]
69 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], float 0.000000e+00, float [[X]]
70 ; CHECK-NEXT: ret float [[COND]]
82 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], double [[X]], double -0.000000e+00
83 ; CHECK-NEXT: ret double [[COND]]
95 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], double -0.000000e+00, double [[X]]
96 ; CHECK-NEXT: ret double [[COND]]
197 ; CHECK-NEXT: [[COND:%.*]] = select ninf nsz i1 [[CMP]], double [[X]], double -0.000000e+00
198 ; CHECK-NEXT: ret double [[COND]]
[all …]
/external/llvm-project/llvm/test/Transforms/EarlyCSE/
Dand_or.ll8 ; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
9 ; CHECK-NEXT: br i1 [[COND]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
33 ; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
34 ; CHECK-NEXT: [[AND_COND:%.*]] = and i1 [[COND]], [[C:%.*]]
39 ; CHECK-NEXT: [[Y:%.*]] = select i1 [[COND]], i32 [[A]], i32 [[B]]
61 ; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
62 ; CHECK-NEXT: [[OR_COND:%.*]] = or i1 [[COND]], [[C:%.*]]
65 ; CHECK-NEXT: [[X:%.*]] = select i1 [[COND]], i32 [[A]], i32 [[B]]
89 ; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
90 ; CHECK-NEXT: [[AND_COND1:%.*]] = and i1 [[COND]], [[C1:%.*]]
[all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dicmp-bc-vec.ll17 ; CHECK-NEXT: [[COND:%.*]] = xor i1 [[VAL:%.*]], true
18 ; CHECK-NEXT: ret i1 [[COND]]
29 ; CHECK-NEXT: [[COND:%.*]] = xor i1 [[VAL:%.*]], true
30 ; CHECK-NEXT: ret i1 [[COND]]
52 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i8 [[VAL:%.*]], 72
53 ; CHECK-NEXT: ret i1 [[COND]]
64 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i8 [[VAL:%.*]], 72
65 ; CHECK-NEXT: ret i1 [[COND]]
79 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[CAST]], 1212696648
80 ; CHECK-NEXT: ret i1 [[COND]]
[all …]
Dselect-ctlz-to-cttz.ll19 ; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.cttz.i32(i32 [[A:%.*]], i1 true), !range !0
20 ; CHECK-NEXT: ret i32 [[COND]]
33 ; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.cttz.i32(i32 [[A:%.*]], i1 false), !range !0
34 ; CHECK-NEXT: ret i32 [[COND]]
47 ; CHECK-NEXT: [[COND:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[A:%.*]], i1 true)
48 ; CHECK-NEXT: ret <2 x i32> [[COND]]
66 ; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.cttz.i32(i32 [[A]], i1 true), !range !0
67 ; CHECK-NEXT: ret i32 [[COND]]
81 ; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.cttz.i32(i32 [[A:%.*]], i1 true), !range !0
82 ; CHECK-NEXT: ret i32 [[COND]]
[all …]
Dpull-conditional-binop-through-shift.ll10 ; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
22 ; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
35 ; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
47 ; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
60 ; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
72 ; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
85 ; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
97 ; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
112 ; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
124 ; CHECK-NEXT: [[R:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]]
[all …]
Dabs_abs.ll8 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
9 ; CHECK-NEXT: ret i32 [[COND]]
24 ; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[SUB]], <2 x i32> [[X]]
25 ; CHECK-NEXT: ret <2 x i32> [[COND]]
40 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
41 ; CHECK-NEXT: ret i32 [[COND]]
56 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
57 ; CHECK-NEXT: ret i32 [[COND]]
72 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
73 ; CHECK-NEXT: ret i32 [[COND]]
[all …]
Dusub-overflow-known-by-implied-cond.ll9 ; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[A:%.*]], [[B:%.*]]
10 ; CHECK-NEXT: br i1 [[COND]], label [[BB3:%.*]], label [[BB1:%.*]]
36 ; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[A:%.*]], [[B:%.*]]
37 ; CHECK-NEXT: br i1 [[COND]], label [[BB3:%.*]], label [[BB1:%.*]]
65 ; CHECK-NEXT: [[COND:%.*]] = icmp ugt i32 [[A:%.*]], [[B:%.*]]
66 ; CHECK-NEXT: br i1 [[COND]], label [[BB1:%.*]], label [[BB3:%.*]]
92 ; CHECK-NEXT: [[COND:%.*]] = icmp ugt i32 [[A:%.*]], [[B:%.*]]
93 ; CHECK-NEXT: br i1 [[COND]], label [[BB1:%.*]], label [[BB3:%.*]]
121 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]]
122 ; CHECK-NEXT: br i1 [[COND]], label [[BB1:%.*]], label [[BB3:%.*]]
[all …]
/external/llvm/test/Transforms/SimplifyCFG/X86/
Dspeculate-cttz-ctlz.ll8 ; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
10 ; ALL-NEXT: select i1 [[COND]], i64 64, i64 [[CTLZ]]
27 ; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
29 ; ALL-NEXT: select i1 [[COND]], i32 32, i32 [[CTLZ]]
47 ; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i16 %A, 0
49 ; ALL-NEXT: select i1 [[COND]], i16 16, i16 [[CTLZ]]
67 ; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
69 ; ALL-NEXT: select i1 [[COND]], i64 64, i64 [[CTTZ]]
87 ; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
89 ; ALL-NEXT: select i1 [[COND]], i32 32, i32 [[CTTZ]]
[all …]
/external/mesa3d/src/gallium/drivers/freedreno/a6xx/
Dfd6_program.c215 COND(ncomp[0] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(1)) | in setup_stream_out()
216 COND(ncomp[1] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(1)) | in setup_stream_out()
217 COND(ncomp[2] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(1)) | in setup_stream_out()
218 COND(ncomp[3] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(1))); in setup_stream_out()
254 OUT_RING(ring, COND(state->hs, in setup_config_stateobj()
257 OUT_RING(ring, COND(state->ds, in setup_config_stateobj()
260 OUT_RING(ring, COND(state->gs, in setup_config_stateobj()
268 OUT_RING(ring, COND(state->vs, A6XX_SP_VS_CONFIG_ENABLED) | in setup_config_stateobj()
274 OUT_RING(ring, COND(state->hs, in setup_config_stateobj()
281 OUT_RING(ring, COND(state->ds, in setup_config_stateobj()
[all …]
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/
Dfd4_program.c270 COND(emit->binning_pass, A4XX_SP_SP_CTRL_REG_BINNING_PASS)); in fd4_program_emit()
274 COND(s[VS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER) | in fd4_program_emit()
275 COND(s[FS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER) | in fd4_program_emit()
276 COND(s[VS].instrlen && s[FS].instrlen, in fd4_program_emit()
289 COND(s[VS].v->need_pixlod, A4XX_SP_VS_CTRL_REG0_PIXLODENABLE)); in fd4_program_emit()
339 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG0_VARYING) | in fd4_program_emit()
358 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG0_VARYING) | in fd4_program_emit()
364 COND(s[FS].v->need_pixlod, A4XX_SP_FS_CTRL_REG0_PIXLODENABLE)); in fd4_program_emit()
367 COND(s[FS].v->frag_face, A4XX_SP_FS_CTRL_REG1_FACENESS) | in fd4_program_emit()
368 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG1_VARYING) | in fd4_program_emit()
[all …]
/external/llvm-project/llvm/test/Transforms/CanonicalizeFreezeInLoops/
Donephi.ll15 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[I_NEXT]], [[N:%.*]]
16 ; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[EXIT:%.*]]
42 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[I_NEXT]], [[N:%.*]]
43 ; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[EXIT:%.*]]
70 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[I_NEXT]], [[N:%.*]]
71 ; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[EXIT:%.*]]
100 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[I_NEXT]], [[N:%.*]]
101 ; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[EXIT:%.*]]
131 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[I_NEXT]], [[N:%.*]]
132 ; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[EXIT:%.*]]
[all …]
/external/llvm-project/mlir/test/Conversion/SPIRVToLLVM/
Dcontrol-flow-ops-to-llvm.mlir35 // CHECK: %[[COND:.*]] = llvm.mlir.constant(true) : !llvm.i1
37 // CHECK: lvm.cond_br %[[COND]], ^bb1, ^bb2
55 // CHECK: ^bb1(%{{.*}}: !llvm.i32, %[[COND:.*]]: !llvm.i1):
57 // CHECK: llvm.cond_br %[[COND]], ^bb3, ^bb4(%{{.*}}, %{{.*}} : !llvm.i32, !llvm.i32)
93 // CHECK: %[[COND:.*]] = llvm.mlir.constant(true) : !llvm.i1
94 // CHECK: llvm.cond_br %[[COND]], ^[[BB2:.*]], ^[[BB4:.*]]
147 // CHECK: %[[COND:.*]] = llvm.mlir.constant(true) : !llvm.i1
149 // CHECK: llvm.cond_br %[[COND]], ^bb1, ^bb2
167 // CHECK: %[[COND:.*]] = llvm.mlir.constant(true) : !llvm.i1
169 // CHECK: llvm.cond_br %[[COND]], ^bb1, ^bb2

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