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Searched refs:COND5 (Results 1 – 3 of 3) sorted by relevance

/external/llvm-project/llvm/test/Transforms/CodeGenPrepare/X86/
Dfreeze-brcond.ll220 ; CHECK-NEXT: [[COND5:%.*]] = and i1 [[F:%.*]], [[COND4]]
221 ; CHECK-NEXT: [[COND6:%.*]] = and i1 [[G:%.*]], [[COND5]]
/external/mesa3d/src/gallium/drivers/radeon/
Dradeon_vcn_dec.h209 #define COND5 5 macro
/external/llvm-project/llvm/test/Transforms/PhaseOrdering/X86/
Dvector-reductions.ll186 ; CHECK-NEXT: [[COND5:%.*]] = zext i1 [[CMP4]] to i32
187 ; CHECK-NEXT: ret i32 [[COND5]]