Searched refs:COND6 (Results 1 – 6 of 6) sorted by relevance
| /external/llvm-project/llvm/test/Transforms/LoopVectorize/ |
| D | pr44488-predication.ll | 73 ; CHECK-NEXT: [[COND6:%.*]] = phi i16 [ [[REM]], [[COND_FALSE4]] ], [ 5786, [[COND_END]] ]
74 ; CHECK-NEXT: store i16 [[COND6]], i16* @v_39, align 1
|
| /external/llvm-project/llvm/test/Transforms/CodeGenPrepare/X86/ |
| D | freeze-brcond.ll | 221 ; CHECK-NEXT: [[COND6:%.*]] = and i1 [[G:%.*]], [[COND5]]
222 ; CHECK-NEXT: [[FR:%.*]] = freeze i1 [[COND6]]
|
| /external/llvm-project/clang/test/CodeGenObjC/ |
| D | arc-ternary-op.m | 185 // CHECK: %[[COND6:.*]] = phi i8** [ %[[ARRAYDECAY]], %{{.*}} ], [ %[[ARRAYDECAY5]], %{{.*}} ]
186 // CHECK: store i8** %[[COND6]], i8*** %[[P]], align 8
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | radeon_vcn_dec.h | 210 #define COND6 6 macro
|
| /external/llvm-project/llvm/test/Transforms/PhaseOrdering/X86/ |
| D | vector-reductions.ll | 79 ; CHECK-NEXT: [[COND6:%.*]] = zext i1 [[CMP5_NOT]] to i32
80 ; CHECK-NEXT: ret i32 [[COND6]]
|
| /external/llvm-project/llvm/test/Transforms/LoopVectorize/ARM/ |
| D | mve-qabs.ll | 252 ; CHECK-NEXT: [[COND6:%.*]] = select i1 [[CMP1]], i32 [[TMP8]], i32 [[COND]]
254 ; CHECK-NEXT: store i32 [[COND6]], i32* [[PDST_ADDR_015]], align 4
|