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Searched refs:CONST1 (Results 1 – 17 of 17) sorted by relevance

/external/turbine/javatests/com/google/turbine/lower/testdata/
Dconst_underscore.test5 public static final long CONST1 = 10_000L;
/external/jacoco/org.jacoco.core.test.validation.java5/src/org/jacoco/core/test/validation/java5/targets/
DInterfaceClassInitializerTarget.java23 static final int CONST1 = 12345; // assertEmpty() field
DClassInitializerTarget.java25 public static final int CONST1 = 3; // assertEmpty() field in ClassInitializerTarget
/external/llvm-project/llvm/test/Transforms/ConstantHoisting/AArch64/
Dconsthoist-unreachable.ll19 ; CHECK-NEXT: [[CONST1:%.*]] = bitcast i32 1232131 to i32
20 ; CHECK-NEXT: store i32 [[CONST1]], i32* @c.a, align 1
/external/llvm-project/llvm/test/Transforms/ConstantHoisting/X86/
Dpr43903-not-all-uses-rebased.ll20 ; CHECK-NEXT: [[CONST1:%.*]] = bitcast i16* getelementptr inbounds ([2 x i16], [2 x i16]* @a, i3…
21 ; CHECK-NEXT: [[CMP:%.*]] = icmp ule i16* undef, [[CONST1]]
Dehpad.ll14 ; BFIHOIST: %[[CONST1:.*]] = bitcast i64 9209618997431186100 to i64
15 ; BFIHOIST: %add = add i64 %call4, %[[CONST1]]
/external/tensorflow/tensorflow/compiler/mlir/tensorflow/tests/
Dtensor_list_ops_decomposition.mlir23 …// CHECK-NEXT: %[[CONST1:.*]] = "tf.Const"() {value = dense<1> : tensor<1xi32>} : () -> tensor<1xi…
24 …// CHECK-NEXT: %[[NEW_SIZE:.*]] = "tf.AddV2"(%[[ZERO]], %[[CONST1]]) : (tensor<1xi32>, tensor<1xi3…
182 // CHECK: %[[CONST1:.*]] = "tf.Const"() {value = dense<1> : tensor<i32>} : () -> tensor<i32>
184 // CHECK: %[[SUB:.*]] = "tf.Sub"(%[[BARG1]], %[[CONST1]])
189 // CHECK: %[[CONST1:.*]] = "tf.Const"() {value = dense<1> : tensor<1xi32>} : () -> tensor<1xi32>
190 // CHECK: %[[ADD:.*]] = "tf.AddV2"(%[[BARG2]], %[[CONST1]])
225 // CHECK: %[[CONST1:.*]] = "tf.Const"() {value = dense<1> : tensor<1xi32>} : () -> tensor<1xi32>
226 // CHECK: %[[ADD:.*]] = "tf.AddV2"(%[[TARG1]], %[[CONST1]])
272 // CHECK: %[[CONST1:.*]] = "tf.Const"() {value = dense<1> : tensor<1xi32>} : () -> tensor<1xi32>
273 // CHECK: %[[ADD:.*]] = "tf.AddV2"(%[[TARG1]], %[[CONST1]])
[all …]
Dstack_ops_decomposition.mlir28 …// CHECK-NEXT: %[[CONST1:.*]] = "tf.Const"() {value = dense<1> : tensor<1xi32>} : () -> tensor<1xi…
29 …// CHECK-NEXT: %[[NEW_SIZE:.*]] = "tf.AddV2"(%[[READ_SIZE]], %[[CONST1]]) : (tensor<1xi32>, tensor…
75 …// CHECK-NEXT: %[[CONST1:.*]] = "tf.Const"() {value = dense<1> : tensor<1xi32>} : () -> tensor<1xi…
76 …// CHECK-NEXT: %[[NEW_SIZE:.*]] = "tf.AddV2"(%[[STACK_SIZE]], %[[CONST1]]) : (tensor<1xi32>, tenso…
105 // CHECK: %[[CONST1:.*]] = "tf.Const"() {value = dense<1> : tensor<i32>} : () -> tensor<i32>
107 // CHECK: %[[SUB:.*]] = "tf.Sub"(%[[BARG1]], %[[CONST1]])
146 // CHECK: %[[CONST1:.*]] = "tf.Const"() {value = dense<1> : tensor<i32>} : () -> tensor<i32>
148 // CHECK: %[[SUB:.*]] = "tf.Sub"(%[[BARG0]], %[[CONST1]])
Dtensor_array_ops_decomposition.mlir260 // CHECK: %[[CONST1:.*]] = "tf.Const"() {value = dense<1> : tensor<i32>} : () -> tensor<i32>
262 // CHECK: %[[SUB:.*]] = "tf.Sub"(%[[BARG1]], %[[CONST1]])
331 // CHECK: %[[CONST1:.*]] = "tf.Const"() {value = dense<1> : tensor<i32>} : () -> tensor<i32>
Dtpu_space_to_depth_pass.mlir67 // CHECK: %[[CONST1:.*]] = "tf.Const"() {value = dense<
69 …// CHECK: %[[TRANSPOSE0:.*]] = "tf.Transpose"(%[[RESHAPE0:.*]], %[[CONST1:.*]]) : (tensor<4x4x2x2x…
Dresource_op_lifting.mlir811 // CHECK: %[[CONST1:.*]] = "tf.Const"
812 // CHECK: %[[SUB:.*]] = "tf.Sub"(%[[READ1]], %[[CONST1]])
/external/llvm/test/Transforms/ConstantHoisting/ARM/
Dconst-addr-no-neg-offset.ll10 ; CHECK-NOT: [[CONST1:%const_mat[0-9]*]] = add i32 %const, -4
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dfadd.f16.ll146 ; VI-DAG: v_mov_b32_e32 v[[CONST1:[0-9]+]], 0x3c00
147 ; VI-DAG: v_add_f16_sdwa v[[R_F16_0:[0-9]+]], v[[A_V2_F16]], v[[CONST1]] dst_sel:WORD_1 dst_unused:…
Dimmv216.ll197 ; VI-DAG: v_mov_b32_e32 [[CONST1:v[0-9]+]], 0x3c00
201 ; VI-DAG: v_add_f16_sdwa v{{[0-9]+}}, [[V_SHR]], [[CONST1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD sr…
219 ; VI-DAG: v_mov_b32_e32 [[CONST1:v[0-9]+]], 0xbc00
223 ; VI-DAG: v_add_f16_sdwa v{{[0-9]+}}, [[V_SHR]], [[CONST1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD sr…
367 ; VI-DAG: v_mov_b32_e32 [[CONST1:v[0-9]+]], 1 ; encoding
371 ; VI-DAG: v_add_f16_sdwa v{{[0-9]+}}, [[V_SHR]], [[CONST1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD sr…
/external/libopus/silk/fixed/x86/
Dburg_modified_FIX_sse4_1.c73 __m128i CONST1 = _mm_set1_epi32(1); in silk_burg_modified_sse4_1() local
178 ATMP_3210 = _mm_add_epi32( ATMP_3210, CONST1 ); in silk_burg_modified_sse4_1()
/external/llvm-project/llvm/test/Transforms/ConstantHoisting/ARM/
Dconst-addr-no-neg-offset.ll13 ; CHECK-NOT: [[CONST1:%const_mat[0-9]*]] = add i32 %const, -4
/external/python/cpython2/Modules/
Dshamodule.c123 #define CONST1 0x5a827999L /* Rounds 0-19 */ macro