Searched refs:CPG_BASE (Results 1 – 11 of 11) sorted by relevance
11 #define CPG_BASE (0xE6150000U) macro14 #define CPG_SMSTPCR2 (CPG_BASE + 0x0138U)16 #define CPG_SRCR2 (CPG_BASE + 0x00B0U)18 #define CPG_MSTPSR2 (CPG_BASE + 0x0040U)20 #define CPG_CPGWPR (CPG_BASE + 0x0900U)22 #define CPG_CPGWPCR (CPG_BASE + 0x0904U)24 #define CPG_SMSTPCR9 (CPG_BASE + 0x0994U)26 #define CPG_MSTPSR9 (CPG_BASE + 0x09A4U)31 #define SCMSTPCR0 (CPG_BASE + 0x0B20U)33 #define SCMSTPCR1 (CPG_BASE + 0x0B24U)[all …]
37 #define CPG_FRQCRB (CPG_BASE + 0x0004U)39 #define CPG_PLLECR (CPG_BASE + 0x00D0U)40 #define CPG_MSTPSR5 (CPG_BASE + 0x003CU)41 #define CPG_SRCR4 (CPG_BASE + 0x00BCU)42 #define CPG_PLL3CR (CPG_BASE + 0x00DCU)43 #define CPG_ZB3CKCR (CPG_BASE + 0x0380U)44 #define CPG_FRQCRD (CPG_BASE + 0x00E4U)45 #define CPG_SMSTPCR5 (CPG_BASE + 0x0144U)46 #define CPG_CPGWPR (CPG_BASE + 0x0900U)47 #define CPG_SRSTCLR4 (CPG_BASE + 0x0950U)
39 #define CPG_FRQCRB (CPG_BASE + 0x0004U)41 #define CPG_PLLECR (CPG_BASE + 0x00D0U)42 #define CPG_MSTPSR5 (CPG_BASE + 0x003CU)43 #define CPG_SRCR4 (CPG_BASE + 0x00BCU)44 #define CPG_PLL3CR (CPG_BASE + 0x00DCU)45 #define CPG_ZB3CKCR (CPG_BASE + 0x0380U)46 #define CPG_FRQCRD (CPG_BASE + 0x00E4U)47 #define CPG_SMSTPCR5 (CPG_BASE + 0x0144U)48 #define CPG_CPGWPR (CPG_BASE + 0x0900U)49 #define CPG_SRSTCLR4 (CPG_BASE + 0x0950U)
245 #define CPG_BASE 0xE6150000U macro246 #define CPG_FRQCRB (CPG_BASE + 0x0004U)247 #define CPG_PLLECR (CPG_BASE + 0x00D0U)248 #define CPG_MSTPSR5 (CPG_BASE + 0x003CU)249 #define CPG_SRCR4 (CPG_BASE + 0x00BCU)250 #define CPG_PLL3CR (CPG_BASE + 0x00DCU)251 #define CPG_ZB3CKCR (CPG_BASE + 0x0380U)252 #define CPG_FRQCRD (CPG_BASE + 0x00E4U)253 #define CPG_SMSTPCR5 (CPG_BASE + 0x0144U)254 #define CPG_CPGWPR (CPG_BASE + 0x0900U)[all …]
54 #define CPG_BASE (0xE6150000U) macro56 #define CPG_MSTPSR3 (CPG_BASE + 0x0048U)58 #define CPG_SMSTPCR3 (CPG_BASE + 0x013CU)60 #define CPG_SD2CKCR (CPG_BASE + 0x0268U)62 #define CPG_SD3CKCR (CPG_BASE + 0x026CU)64 #define CPG_CPGWPR (CPG_BASE + 0x0900U)
222 #define CPG_CA57DBGRCR (CPG_BASE + 0x2180U)223 #define CPG_CA53DBGRCR (CPG_BASE + 0x1180U)225 #define CPG_PLL0CR (CPG_BASE + 0x00D8U)226 #define CPG_PLL2CR (CPG_BASE + 0x002CU)227 #define CPG_PLL4CR (CPG_BASE + 0x01F4U)228 #define CPG_CPGWPCR (CPG_BASE + 0x0904U)
16 #define CPG_BASE 0xE6150000 macro34 cpg = mmio_read_32(CPG_BASE + CPG_MSTPSR3); in rcar_pcie_fixup()
25 #define CPG_BASE (0xE6150000) macro172 ldr x0, =CPG_BASE
452 #define CPG_BASE (0xE6150000U) macro453 #define CPG_MSTPSR0 (CPG_BASE + 0x0030U)454 #define CPG_RMSTPCR0 (CPG_BASE + 0x0110U)
581 #define CPG_BASE (0xE6150000U) macro582 #define CPG_SCMSTPCR0 (CPG_BASE + 0x0B20U)583 #define CPG_MSTPSR0 (CPG_BASE + 0x0030U)