Searched refs:CPG_CPGWPR (Results 1 – 12 of 12) sorted by relevance
| /external/arm-trusted-firmware/drivers/renesas/common/emmc/ |
| D | emmc_init.c | 93 mmio_write_32(CPG_CPGWPR, (~dataL)); in emmc_dev_finalize()
106 mmio_write_32(CPG_CPGWPR, ~((uint32_t) (BIT9 | BIT0))); /* SD phy 200MHz */ in emmc_dev_init()
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| D | emmc_registers.h | 64 #define CPG_CPGWPR (CPG_BASE + 0x0900U) macro
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| /external/arm-trusted-firmware/plat/renesas/common/include/registers/ |
| D | cpg_registers.h | 20 #define CPG_CPGWPR (CPG_BASE + 0x0900U) macro
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| /external/arm-trusted-firmware/drivers/renesas/rcar/ddr/ddr_b/ |
| D | boot_init_dram_regdef.h | 46 #define CPG_CPGWPR (CPG_BASE + 0x0900U) macro
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| D | boot_init_dram.c | 350 mmio_write_32(CPG_CPGWPR, ~v); in cpg_write_32()
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| /external/arm-trusted-firmware/drivers/renesas/common/scif/ |
| D | scif.S | 32 #define CPG_CPGWPR (0x0900) macro
176 str w2, [x0, #CPG_CPGWPR]
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| /external/arm-trusted-firmware/drivers/renesas/rzg/ddr/ddr_b/ |
| D | boot_init_dram_regdef.h | 48 #define CPG_CPGWPR (CPG_BASE + 0x0900U) macro
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| D | boot_init_dram.c | 333 mmio_write_32(CPG_CPGWPR, ~v); in cpg_write_32()
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| /external/arm-trusted-firmware/drivers/renesas/common/ |
| D | ddr_regs.h | 254 #define CPG_CPGWPR (CPG_BASE + 0x0900U) macro
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| /external/arm-trusted-firmware/plat/renesas/rzg/ |
| D | bl2_plat_setup.c | 807 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); in bl2_el3_early_platform_setup()
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| /external/arm-trusted-firmware/drivers/renesas/rcar/ddr/ddr_a/ |
| D | ddr_init_e3.c | 64 mmio_write_32(CPG_CPGWPR, 0x5A5AFFFF); in init_ddr()
867 mmio_write_32(CPG_CPGWPR, 0x5A5AFFFF); in recovery_from_backup_mode()
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| /external/arm-trusted-firmware/plat/renesas/rcar/ |
| D | bl2_plat_setup.c | 962 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); in bl2_el3_early_platform_setup()
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