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Searched refs:CPG_PLLECR (Results 1 – 6 of 6) sorted by relevance

/external/arm-trusted-firmware/drivers/renesas/rcar/ddr/ddr_b/
Dboot_init_dram_regdef.h39 #define CPG_PLLECR (CPG_BASE + 0x00D0U) macro
Dboot_init_dram.c389 data_l = mmio_read_32(CPG_PLLECR) & ~CPG_PLLECR_PLL3E_BIT; in pll3_control()
390 cpg_write_32(CPG_PLLECR, data_l); in pll3_control()
406 data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR); in pll3_control()
407 cpg_write_32(CPG_PLLECR, data_l); in pll3_control()
411 data_l = mmio_read_32(CPG_PLLECR); in pll3_control()
430 data_l = mmio_read_32(CPG_PLLECR); in pll3_control()
446 data_l = mmio_read_32(CPG_PLLECR); in pll3_control()
472 data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR); in pll3_control()
473 cpg_write_32(CPG_PLLECR, data_l); in pll3_control()
477 data_l = mmio_read_32(CPG_PLLECR); in pll3_control()
/external/arm-trusted-firmware/drivers/renesas/rzg/ddr/ddr_b/
Dboot_init_dram_regdef.h41 #define CPG_PLLECR (CPG_BASE + 0x00D0U) macro
Dboot_init_dram.c342 data_l = mmio_read_32(CPG_PLLECR); in wait_for_pll3_status_bit_turned_on()
382 data_l = mmio_read_32(CPG_PLLECR) & ~CPG_PLLECR_PLL3E_BIT; in pll3_control()
383 cpg_write_32(CPG_PLLECR, data_l); in pll3_control()
398 data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR); in pll3_control()
399 cpg_write_32(CPG_PLLECR, data_l); in pll3_control()
/external/arm-trusted-firmware/drivers/renesas/common/
Dddr_regs.h247 #define CPG_PLLECR (CPG_BASE + 0x00D0U) macro
/external/arm-trusted-firmware/drivers/renesas/rcar/ddr/ddr_a/
Dddr_init_e3.c70 while (!(mmio_read_32(CPG_PLLECR) & BIT(11))) in init_ddr()
873 while (!(mmio_read_32(CPG_PLLECR) & BIT(11))) in recovery_from_backup_mode()