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Searched refs:CPU_INTR_S_SET (Results 1 – 5 of 5) sorted by relevance

/external/arm-trusted-firmware/plat/socionext/synquacer/drivers/mhu/
Dsq_mhu.c25 #define CPU_INTR_S_SET 0x308 macro
56 mmio_write_32(PLAT_SQ_MHU_BASE + CPU_INTR_S_SET, 1 << slot_id); in mhu_secure_message_send()
/external/arm-trusted-firmware/drivers/arm/css/mhu/
Dcss_mhu.c24 #define CPU_INTR_S_SET 0x308 macro
59 mmio_write_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_SET, 1 << slot_id); in mhu_secure_message_send()
/external/arm-trusted-firmware/plat/brcm/common/
Dbrcm_mhu.c27 #define CPU_INTR_S_SET CRMU_IHOST_SW_PERSISTENT_REG10 macro
68 mmio_setbits_32(PLAT_BRCM_MHU_BASE + CPU_INTR_S_SET, 1 << slot_id); in mhu_secure_message_send()
/external/arm-trusted-firmware/plat/arm/board/corstone700/common/drivers/mhu/
Dmhu.h14 #define CPU_INTR_S_SET 0x0C macro
Dmhu.c91 mmio_write_32(address + CPU_INTR_S_SET, message); in mhu_secure_message_send()