Searched refs:CPU_INTR_S_STAT (Results 1 – 5 of 5) sorted by relevance
24 #define CPU_INTR_S_STAT 0x300 macro44 while (mmio_read_32(PLAT_SQ_MHU_BASE + CPU_INTR_S_STAT) & in mhu_secure_message_start()52 assert(!(mmio_read_32(PLAT_SQ_MHU_BASE + CPU_INTR_S_STAT) & in mhu_secure_message_send()92 assert(mmio_read_32(PLAT_SQ_MHU_BASE + CPU_INTR_S_STAT) == 0); in mhu_secure_init()
23 #define CPU_INTR_S_STAT 0x300 macro47 while (mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) & in mhu_secure_message_start()55 assert(!(mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) & in mhu_secure_message_send()94 assert(mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) == 0); in mhu_secure_init()
26 #define CPU_INTR_S_STAT CRMU_IHOST_SW_PERSISTENT_REG10 macro48 if (!(mmio_read_32(PLAT_BRCM_MHU_BASE + CPU_INTR_S_STAT) & in mhu_secure_message_start()64 assert(!(mmio_read_32(PLAT_BRCM_MHU_BASE + CPU_INTR_S_STAT) & in mhu_secure_message_send()124 mmio_write_32(PLAT_BRCM_MHU_BASE + CPU_INTR_S_STAT, 0); in mhu_secure_init()
47 intr_stat_check = (mmio_read_32(address + CPU_INTR_S_STAT) & in mhu_secure_message_start()71 assert((mmio_read_32(address + CPU_INTR_S_STAT) & in mhu_secure_message_send()116 assert(mmio_read_32(PLAT_SDK700_MHU0_SEND + CPU_INTR_S_STAT) == 0); in mhu_secure_init()
13 #define CPU_INTR_S_STAT 0x00 macro