| /external/llvm/test/CodeGen/PowerPC/ |
| D | opt-cmp-inst-cr0-live.ll | 8 ; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def,dead>;
12 ; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def>;
13 ; CHECK: COPY %CR0
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenAsmWriter.inc | 7771 // (BCC 12, CR0, condbrtarget:$dst) - 4
7773 {AliasPatternCond::K_Reg, PPC::CR0},
7777 // (BCC 14, CR0, condbrtarget:$dst) - 8
7779 {AliasPatternCond::K_Reg, PPC::CR0},
7783 // (BCC 15, CR0, condbrtarget:$dst) - 12
7785 {AliasPatternCond::K_Reg, PPC::CR0},
7789 // (BCC 44, CR0, condbrtarget:$dst) - 16
7791 {AliasPatternCond::K_Reg, PPC::CR0},
7795 // (BCC 46, CR0, condbrtarget:$dst) - 20
7797 {AliasPatternCond::K_Reg, PPC::CR0},
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrHTM.td | 30 let Defs = [CR0] in {
90 // All HTM instructions, with the exception of tcheck, set CR0 with the
92 // instruction is executed. For tbegin., the EQ bit in CR0 can be used
|
| D | PPCInstrInfo.td | 963 let Defs = [CR0] in
978 let Defs = [CARRY, CR0] in
993 let Defs = [CARRY, CR0] in
1007 let Defs = [CR0] in
1021 let Defs = [CR0] in
1037 let Defs = [CR0] in
1047 let Defs = [XER, CR0] in
1063 let Defs = [CR0] in
1074 let Defs = [XER, CR0] in
1089 let Defs = [CARRY, CR0] in
[all …]
|
| D | PPCRegisterInfo.h | 30 Reg = PPC::CR0; in getCRFromCRBit()
|
| /external/capstone/arch/PowerPC/ |
| D | PPCGenAsmWriter.inc | 4997 // (BCC 12, CR0, condbrtarget:$dst)
5014 // (BCC 14, CR0, condbrtarget:$dst)
5031 // (BCC 15, CR0, condbrtarget:$dst)
5048 // (BCC 44, CR0, condbrtarget:$dst)
5065 // (BCC 46, CR0, condbrtarget:$dst)
5082 // (BCC 47, CR0, condbrtarget:$dst)
5099 // (BCC 76, CR0, condbrtarget:$dst)
5116 // (BCC 78, CR0, condbrtarget:$dst)
5133 // (BCC 79, CR0, condbrtarget:$dst)
5150 // (BCC 68, CR0, condbrtarget:$dst)
[all …]
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCInstrHTM.td | 30 let Defs = [CR0] in {
90 // All HTM instructions, with the exception of tcheck, set CR0 with the
92 // instruction is executed. For tbegin., the EQ bit in CR0 can be used
|
| D | PPCInstrInfo.td | 1129 let Defs = [CR0] in
1144 let Defs = [CARRY, CR0] in
1159 let Defs = [CARRY, CR0] in
1173 let Defs = [CR0] in
1187 let Defs = [CR0] in
1203 let Defs = [CR0] in
1213 let Defs = [XER, CR0] in
1229 let Defs = [CR0] in
1240 let Defs = [XER, CR0] in
1255 let Defs = [CARRY, CR0] in
[all …]
|
| D | PPCRegisterInfo.h | 30 Reg = PPC::CR0; in getCRFromCRBit()
|
| /external/llvm-project/clang/lib/Headers/ |
| D | htmintrin.h | 26 #define _HTM_STATE(CR0) ((CR0 >> 1) & 0x3) argument
|
| /external/clang/lib/Headers/ |
| D | htmintrin.h | 40 #define _HTM_STATE(CR0) ((CR0 >> 1) & 0x3) argument
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrHTM.td | 89 // All HTM instructions, with the exception of tcheck, set CR0 with the
91 // instruction is executed. For tbegin., the EQ bit in CR0 can be used
|
| D | PPCInstrInfo.td | 807 let Defs = [CR0] in
822 let Defs = [CARRY, CR0] in
837 let Defs = [CARRY, CR0] in
851 let Defs = [CR0] in
865 let Defs = [CR0] in
881 let Defs = [CR0] in
897 let Defs = [CARRY, CR0] in
911 let Defs = [CR0] in
926 let Defs = [CARRY, CR0] in
940 let Defs = [CR0] in
[all …]
|
| D | PPCRegisterInfo.h | 30 Reg = PPC::CR0; in getCRFromCRBit()
|
| /external/kernel-headers/original/uapi/asm-generic/ |
| D | termbits.h | 92 #define CR0 0000000 macro
|
| /external/llvm/lib/Transforms/Scalar/ |
| D | GuardWidening.cpp | 416 ConstantRange CR0 = in widenCondCommon() local
430 auto SubsetIntersect = CR0.inverse().unionWith(CR1.inverse()).inverse(); in widenCondCommon()
431 auto SupersetIntersect = CR0.intersectWith(CR1); in widenCondCommon()
|
| /external/llvm/test/CodeGen/X86/ |
| D | ipra-reg-usage.ll | 6 …ters: CS DS EFLAGS EIP EIZ ES FPSW FS GS IP RIP RIZ SS BND0 BND1 BND2 BND3 CR0 CR1 CR2 CR3 CR4 CR5…
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCCodeEmitter.cpp | 242 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); in get_crbitm_encoding()
269 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); in getMachineOpValue()
|
| /external/python/cpython2/Modules/ |
| D | termios.c | 447 #ifdef CR0
448 {"CR0", CR0},
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/ |
| D | GuardWidening.cpp | 513 ConstantRange CR0 = in widenCondCommon() local
527 auto SubsetIntersect = CR0.inverse().unionWith(CR1.inverse()).inverse(); in widenCondCommon()
528 auto SupersetIntersect = CR0.intersectWith(CR1); in widenCondCommon()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/DebugInfo/CodeView/ |
| D | CodeViewRegisters.def | 30 #pragma push_macro("CR0")
93 CV_REGISTER(CR0, 80)
361 #pragma pop_macro("CR0")
|
| /external/llvm-project/llvm/lib/Transforms/Scalar/ |
| D | GuardWidening.cpp | 513 ConstantRange CR0 = in widenCondCommon() local
527 auto SubsetIntersect = CR0.inverse().unionWith(CR1.inverse()).inverse(); in widenCondCommon()
528 auto SupersetIntersect = CR0.intersectWith(CR1); in widenCondCommon()
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCCodeEmitter.cpp | 349 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); in get_crbitm_encoding()
363 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); in getMachineOpValue()
|
| /external/llvm-project/llvm/include/llvm/DebugInfo/CodeView/ |
| D | CodeViewRegisters.def | 31 #pragma push_macro("CR0")
94 CV_REGISTER(CR0, 80)
362 #pragma pop_macro("CR0")
|
| /external/python/cpython2/Lib/plat-irix5/ |
| D | IOCTL.py | 107 CR0 = 0 variable
|