Searched refs:CRU_GLB_RST_CON (Results 1 – 9 of 9) sorted by relevance
91 tmp = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON); in soc_reset_config_all()93 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, tmp); in soc_reset_config_all()109 tmp = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON); in px30_soc_reset_config()111 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, tmp); in px30_soc_reset_config()
57 #define CRU_GLB_RST_CON 0xc0 macro
211 temp_val = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON); in rockchip_soc_soft_reset()214 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, temp_val); in rockchip_soc_soft_reset()
51 #define CRU_GLB_RST_CON 0x1f0 macro
197 temp_val = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON) | in rockchip_soc_soft_reset()200 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, temp_val); in rockchip_soc_soft_reset()
89 #define CRU_GLB_RST_CON 0x388 macro
186 #define CRU_GLB_RST_CON 0x0510 macro
325 mmio_clrbits_32(CRU_BASE + CRU_GLB_RST_CON, in soc_global_soft_reset_init()
485 mmio_clrsetbits_32(CRU_BASE + CRU_GLB_RST_CON, 0x3, 0x3); in dram_all_config()666 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, 1 << 1); in pmusram_enable_watchdog()