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Searched refs:CSE (Results 1 – 25 of 181) sorted by relevance

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/external/llvm-project/mlir/test/Pass/
Dir-printing.mlir17 // BEFORE: *** IR Dump Before{{.*}}CSE ***
19 // BEFORE: *** IR Dump Before{{.*}}CSE ***
24 // BEFORE_ALL: *** IR Dump Before{{.*}}CSE ***
28 // BEFORE_ALL: *** IR Dump Before{{.*}}CSE ***
35 // AFTER: *** IR Dump After{{.*}}CSE ***
37 // AFTER: *** IR Dump After{{.*}}CSE ***
42 // AFTER_ALL: *** IR Dump After{{.*}}CSE ***
46 // AFTER_ALL: *** IR Dump After{{.*}}CSE ***
51 // BEFORE_MODULE: *** IR Dump Before{{.*}}CSE *** ('func' operation: @foo)
54 // BEFORE_MODULE: *** IR Dump Before{{.*}}CSE *** ('func' operation: @bar)
[all …]
Dpass-timing.mlir11 // LIST-DAG: CSE
19 // PIPELINE-NEXT: CSE
22 // PIPELINE-NEXT: CSE
30 // MT_LIST-DAG: CSE
38 // MT_PIPELINE-NEXT: CSE
41 // MT_PIPELINE-NEXT: CSE
Ddynamic-pipeline-nested.mlir17 // CSE" output: one for each of the function. If we don't nest, then we expect
18 // the CSE pass to run on the `inner_mod1` module directly.
20 // CHECK: Dump Before CSE
25 // NESTED: Dump Before CSE
Ddynamic-pipeline.mlir16 // MOD1: Dump Before CSE
23 // MOD1: Dump Before CSE
37 // MOD2: Dump Before CSE
/external/llvm-project/mlir/lib/Transforms/
DCSE.cpp49 struct CSE : public CSEBase<CSE> { struct
91 LogicalResult CSE::simplifyOperation(ScopedMapTy &knownValues, Operation *op) { in simplifyOperation()
138 void CSE::simplifyBlock(ScopedMapTy &knownValues, DominanceInfo &domInfo, in simplifyBlock()
161 void CSE::simplifyRegion(ScopedMapTy &knownValues, DominanceInfo &domInfo, in simplifyRegion()
214 void CSE::runOnOperation() { in runOnOperation()
236 std::unique_ptr<Pass> mlir::createCSEPass() { return std::make_unique<CSE>(); } in createCSEPass()
/external/llvm-project/llvm/test/Transforms/EarlyCSE/AMDGPU/
Dintrinsics.ll15 ; CHECK: [[CSE:%[a-z0-9A-Z]+]] = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %in, i32 0, i32 …
16 ; CHECK: add i32 [[CSE]], [[CSE]]
26 ; CHECK: [[CSE:%[a-z0-9A-Z]+]] = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %in, i32 4, i32 …
27 ; CHECK: add i32 [[CSE]], [[CSE]]
/external/llvm/test/Other/
Dopt-bisect-legacy-pass-manager.ll86 ; RUN: %s 2>&1 | FileCheck %s --check-prefix=CHECK-EARLY-CSE
87 ; CHECK-EARLY-CSE: BISECT: running pass ({{[0-9]+}}) Early CSE on function (f1)
88 ; CHECK-EARLY-CSE: BISECT: running pass ({{[0-9]+}}) Early CSE on function (f2)
89 ; CHECK-EARLY-CSE: BISECT: running pass ({{[0-9]+}}) Early CSE on function (f3)
92 ; RUN: 2>&1 | FileCheck %s --check-prefix=CHECK-NOT-EARLY-CSE
93 ; CHECK-NOT-EARLY-CSE: BISECT: NOT running pass ({{[0-9]+}}) Early CSE on function (f1)
94 ; CHECK-NOT-EARLY-CSE: BISECT: NOT running pass ({{[0-9]+}}) Early CSE on function (f2)
95 ; CHECK-NOT-EARLY-CSE: BISECT: NOT running pass ({{[0-9]+}}) Early CSE on function (f3)
/external/llvm-project/llvm/test/Other/
Dopt-bisect-legacy-pass-manager.ll87 ; RUN: %s 2>&1 | FileCheck %s --check-prefix=CHECK-EARLY-CSE
88 ; CHECK-EARLY-CSE: BISECT: running pass ({{[0-9]+}}) Early CSE on function (f1)
89 ; CHECK-EARLY-CSE: BISECT: running pass ({{[0-9]+}}) Early CSE on function (f2)
90 ; CHECK-EARLY-CSE: BISECT: running pass ({{[0-9]+}}) Early CSE on function (f3)
93 ; RUN: %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOT-EARLY-CSE
94 ; CHECK-NOT-EARLY-CSE: BISECT: NOT running pass ({{[0-9]+}}) Early CSE on function (f1)
95 ; CHECK-NOT-EARLY-CSE: BISECT: NOT running pass ({{[0-9]+}}) Early CSE on function (f2)
96 ; CHECK-NOT-EARLY-CSE: BISECT: NOT running pass ({{[0-9]+}}) Early CSE on function (f3)
Dinvariant.group.ll6 ; These tests checks if passes with CSE functionality can do CSE on
17 ; FIXME: This one could be CSE
Dopt-pipeline-vector-passes.ll30 ; OLDPM_O2_EXTRA: Early CSE
38 ; OLDPM_O2_EXTRA: Early CSE
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Dlegalize-ext-csedebug-output.mir22 ; CHECK: CSEInfo::CSE Hit for Opc {{[0-9]+}} : 1
23 ; CHECK: CSEInfo::CSE Hit for Opc {{[0-9]+}} : 1
24 ; CHECK: CSEInfo::CSE Hit for Opc {{[0-9]+}} : 1
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/DebugInfo/CodeView/
DDebugSubsectionVisitor.h49 visitCrossModuleExports(DebugCrossModuleExportsSubsectionRef &CSE,
52 visitCrossModuleImports(DebugCrossModuleImportsSubsectionRef &CSE,
58 virtual Error visitSymbols(DebugSymbolsSubsectionRef &CSE,
/external/llvm-project/llvm/include/llvm/DebugInfo/CodeView/
DDebugSubsectionVisitor.h46 visitCrossModuleExports(DebugCrossModuleExportsSubsectionRef &CSE,
49 visitCrossModuleImports(DebugCrossModuleImportsSubsectionRef &CSE,
55 virtual Error visitSymbols(DebugSymbolsSubsectionRef &CSE,
/external/llvm/docs/HistoricalNotes/
D2001-06-01-GCCOptimizations.txt16 3 . Compute live ranges for CSE
18 5 . [t] CSE
27 14. [t] CSE
45 certainly want to move LLVM emission from step 8 down until at least CSE
/external/llvm-project/llvm/docs/HistoricalNotes/
D2001-06-01-GCCOptimizations.txt16 3 . Compute live ranges for CSE
18 5 . [t] CSE
27 14. [t] CSE
45 certainly want to move LLVM emission from step 8 down until at least CSE
/external/llvm-project/clang/lib/Sema/
DSemaConcept.cpp570 } else if (auto *CSE = dyn_cast<ConceptSpecializationExpr>(SubstExpr)) { in diagnoseWellFormedUnsatisfiedConstraintExpr() local
571 if (CSE->getTemplateArgsAsWritten()->NumTemplateArgs == 1) { in diagnoseWellFormedUnsatisfiedConstraintExpr()
573 CSE->getSourceRange().getBegin(), in diagnoseWellFormedUnsatisfiedConstraintExpr()
577 << CSE->getTemplateArgsAsWritten()->arguments()[0].getArgument() in diagnoseWellFormedUnsatisfiedConstraintExpr()
578 << CSE->getNamedConcept(); in diagnoseWellFormedUnsatisfiedConstraintExpr()
582 << (int)First << CSE; in diagnoseWellFormedUnsatisfiedConstraintExpr()
584 S.DiagnoseUnsatisfiedConstraint(CSE->getSatisfaction()); in diagnoseWellFormedUnsatisfiedConstraintExpr()
762 } else if (auto *CSE = dyn_cast<const ConceptSpecializationExpr>(E)) { in fromConstraintExpr() local
766 S, CSE->getExprLoc(), in fromConstraintExpr()
768 CSE->getSourceRange()); in fromConstraintExpr()
[all …]
/external/tensorflow/tensorflow/compiler/mlir/tensorflow/tests/
Dtf_executor_ops_side_effect.mlir2 // Checks that CSE runs without generating invalid IR and doesn't CSE ops like
/external/llvm-project/llvm/test/Transforms/EarlyCSE/
Dconditional.ll4 ; Can we CSE a known condition to a constant?
24 ; We can CSE the condition, but we *don't* know it's value after the merge
59 ; Replace a use rather than CSE
/external/llvm/test/Transforms/EarlyCSE/
Dconditional.ll3 ; Can we CSE a known condition to a constant?
23 ; We can CSE the condition, but we *don't* know it's value after the merge
58 ; Replace a use rather than CSE
/external/llvm-project/llvm/test/Analysis/MemorySSA/
Dpr36883.ll12 %load1 = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %p, i32 2) #4 ; load CSE replacement
22 %load3 = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %p, i32 2) #4 ; load CSE removed
/external/llvm-project/llvm/test/CodeGen/AArch64/
Darm64-cse.ll5 ; CSE between "icmp reg reg" and "sub reg reg".
36 ; CSE between "icmp reg imm" and "sub reg imm".
/external/llvm/test/CodeGen/AArch64/
Darm64-cse.ll5 ; CSE between "icmp reg reg" and "sub reg reg".
36 ; CSE between "icmp reg imm" and "sub reg imm".
/external/llvm-project/llvm/test/CodeGen/X86/
Drdrand.ll59 define i32 @CSE() nounwind {
60 ; X86-LABEL: CSE:
67 ; X64-LABEL: CSE:
/external/llvm-project/llvm/test/DebugInfo/MIR/X86/
Dmachine-cse.mir5 # two (MIR) function that have SHL/LEA instructions CSE'd in the bb.1.bb1 block.
8 # In the first (@t) there's only one use of %100, and that gets CSE'd away. The
121 ; Check for CSE happening and DBG_VALUE updating.
185 ; CSE should happen, DBG_VALUE updating should not.
/external/llvm/test/Transforms/EarlyCSE/AArch64/
Dintrinsics.ll6 ; Check that @llvm.aarch64.neon.ld2 is optimized away by Early CSE.
40 ; Check that the first @llvm.aarch64.neon.st2 is optimized away by Early CSE.
76 ; Check that the first @llvm.aarch64.neon.ld2 is optimized away by Early CSE.
111 ; away by Early CSE.
146 ; Check that @llvm.aarch64.neon.ld3 is not optimized away by Early CSE due
181 ; Check that @llvm.aarch64.neon.st3 is not optimized away by Early CSE due to

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